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    Semiconductor device having chip selection circuit and method of generating chip selection signal
    11.
    发明授权
    Semiconductor device having chip selection circuit and method of generating chip selection signal 有权

    公开(公告)号：US06643191B2

    公开(公告)日：2003-11-04

    申请号：US10102308

    申请日：2002-03-19

    Applicant: Yun-sang Lee ,  Jong-hyun Choi ,  Sang-seok Kang

    Inventor： Yun-sang Lee ,  Jong-hyun Choi ,  Sang-seok Kang

    IPC: G11C700

    CPC classification number: G11C29/44 ,  G11C8/12

    Abstract: A semiconductor memory device and a method of generating a chip selection signal that enable the analysis of the causes of defects of defective memory devices selected by a user from a system with a plurality of memory devices and the fixing the defects are provided. The semiconductor memory device includes a programming register, an input buffer control circuit, and a chip selection circuit. The programming register activates an output signal in response to an address and a command input from the outside. The input buffer control circuit activates the plurality of data input buffer circuits in response to the output signal of the programming register. The chip selection circuit activates a defect detecting & repairing circuit, such as a repair circuit or a test time shortening circuit, when at least one of output signals of the plurality of data input buffer circuits is in a first logic state.

    Memory system having variable operating voltage and related method of operation
    12.
    发明授权
    Memory system having variable operating voltage and related method of operation 有权
    具有可变工作电压和相关操作方法的存储器系统

    公开(公告)号：US09076542B2

    公开(公告)日：2015-07-07

    申请号：US14077274

    申请日：2013-11-12

    Applicant: Dong Hyun Sohn ,  Chan Kyung Kim ,  Yun Sang Lee

    Inventor： Dong Hyun Sohn ,  Chan Kyung Kim ,  Yun Sang Lee

    IPC: G11C11/00 ,  G11C11/14 ,  G11C11/36 ,  G11C11/16

    CPC classification number: G11C11/1697 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

    Abstract: A magneto-resistive random access memory (MRAM) including an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit including a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.

    Abstract translation: 包括具有MRAM单元的MRAM单元阵列的磁阻随机存取存储器（MRAM）以及被配置为产生MRAM单元的反向偏置电压的控制和电压产生单元。 所述控制和电压产生单元包括命令解码器，其被配置为响应于从存储器控制器输出的命令产生解码信号;以及电压控制器和发生器，其被配置为基于所述解码信号产生具有幅度的所述反向偏置电压，以及 从存储器控制器输出的复位信号。

    MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    16.
    发明申请
    MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 失效
    存储单元阵列和包括其的半导体存储器件

    公开(公告)号：US20090147559A1

    公开(公告)日：2009-06-11

    申请号：US12326940

    申请日：2008-12-03

    Applicant: Yun-Sang LEE ,  Woo-Jung SUN ,  Jung-Bae LEE

    Inventor： Yun-Sang LEE ,  Woo-Jung SUN ,  Jung-Bae LEE

    IPC: G11C11/4091 ,  G11C7/06

    CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

    Abstract: A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.

    Abstract translation: 具有开放位线结构的存储单元阵列包括第一子存储单元阵列，第二子存储单元阵列，读出放大器/预充电电路，第一电容器和第二电容器。 第一子存储单元阵列响应于第一字线使能信号被激活，并且第二子存储单元阵列响应于第二字线使能信号被激活。 感测放大器/预充电电路通过第一位线连接到第一子存储单元阵列，并通过第二位线连接到第二子存储单元阵列，并且读出放大器/预充电电路对第一位线和第二位进行预充电 并且放大从第一子存储单元阵列和第二子存储单元阵列提供的数据。

    Semiconductor memory device and redundancy method of the same
    17.
    发明授权
    Semiconductor memory device and redundancy method of the same 有权
    半导体存储器件和冗余方法相同

    公开(公告)号：US07535780B2

    公开(公告)日：2009-05-19

    申请号：US11723473

    申请日：2007-03-20

    Applicant: Yun-Sang Lee

    Inventor： Yun-Sang Lee

    IPC: G11C29/00

    CPC classification number: G06F11/1016 ,  G11C29/42 ,  G11C29/44 ,  G11C29/80 ,  G11C2029/0411 ,  G11C2029/1208

    Abstract: A semiconductor memory device may include a memory cell array, a redundancy address decoder, a defective address detection unit, and a defective address program unit. The memory cell array includes a plurality of memory cell groups and a predetermined number of redundancy memory cell groups. The redundancy address decoder includes a predetermined number of redundancy decoders for accessing at least one group of the redundancy memory cell groups when a first defective address is identical to an externally applied address. The defective address detection unit performs a write operation and a read operation on the memory cell array during a test operation to detect a defective address, and outputs the detected defective address as the first defective address when the same defective address is detected a predetermined number of times or more. The defective address program unit receives and programs the first defective address output from the defective address detection unit during a program operation.

    Abstract translation: 半导体存储器件可以包括存储单元阵列，冗余地址解码器，缺陷地址检测单元和缺陷地址程序单元。 存储单元阵列包括多个存储单元组和预定数量的冗余存储单元组。 冗余地址解码器包括预定数量的冗余解码器，用于当第一缺陷地址与外部施加的地址相同时，用于访问至少一组冗余存储单元组。 缺陷地址检测单元在测试操作期间对存储单元阵列执行写入操作和读取操作以检测缺陷地址，并且当检测到相同的缺陷地址时，将检测到的缺陷地址作为第一缺陷地址输出到预定数量的 次以上。 缺陷地址程序单元在编程操作期间接收并编程从缺陷地址检测单元输出的第一缺陷地址。

    Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same
    18.
    发明申请
    Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same 有权
    在使用其的半导体存储器件和半导体存储器件中提供电源电压的方法

    公开(公告)号：US20090067217A1

    公开(公告)日：2009-03-12

    申请号：US12071348

    申请日：2008-02-20

    Applicant: Jung Sunwoo ,  Yun-Sang Lee

    Inventor： Jung Sunwoo ,  Yun-Sang Lee

    IPC: G11C11/24 ,  G11C5/14 ,  G11C8/08

    CPC classification number: G11C5/147 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4074 ,  G11C11/4096

    Abstract: In a method for supplying power supply voltages in a semiconductor memory device a first source voltage is applied to a memory cell of a memory cell array as a cell array internal voltage for operating a sense amplifier coupled to the memory cell. A second source voltage is applied as a word line drive voltage of the memory cell array. The second source voltage has a voltage level higher than a voltage level of the first source voltage. The second source voltage is also applied as a drive voltage of an input/output line driver to drive write data into an input/output line in a write operating mode.

    Abstract translation: 在用于在半导体存储器件中提供电源电压的方法中，第一源电压被施加到存储单元阵列的存储单元，作为用于操作耦合到存储单元的读出放大器的单元阵列内部电压。 施加第二源电压作为存储单元阵列的字线驱动电压。 第二源电压具有高于第一源电压的电压电平的电压电平。 第二源电压也作为输入/输出线驱动器的驱动电压施加，以在写操作模式下将写数据驱动到输入/输出线。

    Semiconductor memory device with auto refresh to specified bank
    19.
    发明授权
    Semiconductor memory device with auto refresh to specified bank 有权
    具有自动刷新到指定银行的半导体存储器件

    公开(公告)号：US07145828B2

    公开(公告)日：2006-12-05

    申请号：US11105169

    申请日：2005-04-12

    Applicant: Yun-Sang Lee ,  Jung-Bae Lee

    Inventor： Yun-Sang Lee ,  Jung-Bae Lee

    IPC: G11C7/00

    CPC classification number: G11C11/40611 ,  G11C11/406 ,  G11C11/40618

    Abstract: Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

    Abstract translation: 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。 该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。 描述和要求保护其他实施例。

    Semiconductor memory devices in which the number of memory banks to be refreshed may be changed and methods of operating the same
    20.
    发明申请
    Semiconductor memory devices in which the number of memory banks to be refreshed may be changed and methods of operating the same 有权
    可以改变其中要刷新的存储体的数量的半导体存储器件及其操作方法

    公开(公告)号：US20060044914A1

    公开(公告)日：2006-03-02

    申请号：US11214657

    申请日：2005-08-30

    Applicant: Sung-ho Choi ,  Yun-sang Lee

    Inventor： Sung-ho Choi ,  Yun-sang Lee

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C11/40618

    Abstract: A semiconductor memory device includes a plurality of memory banks. A refresh control block is responsive to a control address that identifies at least one of the plurality of memory banks to be refreshed. The refresh control block is configured to control refreshing of the at least one of the plurality of memory banks to be refreshed. The control address is used during read and/or write operations of the plurality of memory banks.

    Abstract translation: 半导体存储器件包括多个存储体。 刷新控制块响应于识别要刷新的多个存储器组中的至少一个的控制地址。 刷新控制块被配置为控制要刷新的多个存储体中的至少一个的刷新。 在多个存储体的读取和/或写入操作期间使用控制地址。

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