公开(公告)号：US20140181414A1

公开(公告)日：2014-06-26

申请号：US14055869

申请日：2013-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二组写入请求，指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

公开(公告)号：US09766936B2

公开(公告)日：2017-09-19

申请号：US14935056

申请日：2015-11-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/50 ,  G06F12/0875

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.

公开(公告)号：US09552294B2

公开(公告)日：2017-01-24

申请号：US13736063

申请日：2013-01-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Jaewoong Sim ,  Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0888

Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory.

Abstract translation: 所描述的实施例包括具有包括模式设置机制的高速缓存控制器的主存储器和高速缓冲存储器（或“高速缓存”）。 在一些实施例中，模式设置机制被配置为动态地确定主存储器的访问模式。 基于确定的访问模式，模式设置机制以回写模式配置主存储器的至少一个区域，并以直通模式配置主存储器的其他区域。 在这些实施例中，当在高速缓冲存储器中执行写入操作时，高速缓存控制器确定高速缓存块所处的主存储器中的区域是否配置在回写模式或直写模式中，然后执行相应的 在高速缓存中写入操作。

公开(公告)号：US09251069B2

公开(公告)日：2016-02-02

申请号：US14055869

申请日：2013-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二存储体写入请求以指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

公开(公告)号：US09065722B2

公开(公告)日：2015-06-23

申请号：US13726142

申请日：2012-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: G06F17/50 ,  H04L12/755 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H04L12/701 ,  H01L25/18

CPC classification number: H04L45/021 ,  G06F17/5068 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1461 ,  H01L2924/15192 ,  H04L45/00 ,  H01L2924/00

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

Abstract translation: 电子组件包括设置在插入器处的水平堆叠的管芯，并且还可以包括垂直堆叠的管芯。 堆叠的管芯通过被划分成链路分区和路由器分区的多跳通信网络相互连接。 连接分隔件至少部分地实现在用于水平堆叠的模具的插入件的金属层中。 链路分区还可以部分地由单个管芯中的管芯内互连和通过垂直堆叠的管芯组连接的晶片间互连来实现。 路由器分区在设置在插入器处的部分或全部芯片上实现，并且包括支持通过链路分区的互连来在处理系统的组件之间路由分组的功能的逻辑。 路由器分区可以实现固定路由，或者可以使用可编程路由表或可配置逻辑块来配置。

公开(公告)号：US20140223445A1

公开(公告)日：2014-08-07

申请号：US13761985

申请日：2013-02-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.

Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制被配置为在从一组表中选择的表中执行查找，以从资源集合中识别资源。 当所识别的资源不可用于执行操作并且直到选择资源来执行操作时，选择机制被配置为识别表中的下一个资源，并且当下一个资源可用时选择用于执行操作的下一个资源 用于执行操作。