公开(公告)号：US20160049181A1

公开(公告)日：2016-02-18

申请号：US14460550

申请日：2014-08-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Syed Ali Jafri ,  Yasuko Eckert ,  Srilatha Manne ,  Mithuna S. Thottethodi

IPC: G11C7/10 ,  G06F12/10 ,  G11C11/406

CPC classification number: G06F12/1009 ,  G06F2212/1024 ,  G06F2212/654 ,  G06F2212/655 ,  G06F2212/656

Abstract: Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.

Abstract translation: 描述了通过分析对虚拟存储器页面的存储器绑定访问的序列，确定所访问的虚拟存储器页面之间的连续程度以及访问的虚拟存储器页面的映射集合来将虚拟存储器页面映射到物理存储器页面的方法和系统的实施例 存储页面到相应的单个物理存储器页面。 还描述了用于通过分析虚拟存储器访问的模式以识别所访问的虚拟存储器页的邻接性，基于该模式来预测所访问的虚拟存储器页的邻接性的方法来增加虚拟存储器系统中对DRAM的存储器访问的局部性的方法，以及 将所识别的和预测的连续虚拟存储器页面映射到相应的单个物理存储器页面。

公开(公告)号：US20150357306A1

公开(公告)日：2015-12-10

申请号：US14715023

申请日：2015-05-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: H01L25/065 ,  H01L23/498 ,  H04L12/755 ,  H01L23/48

CPC classification number: H04L45/021 ,  G06F17/5068 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1461 ,  H01L2924/15192 ,  H04L45/00 ,  H01L2924/00

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

Abstract translation: 电子组件包括设置在插入器处的水平堆叠的管芯，并且还可以包括垂直堆叠的管芯。 堆叠的管芯通过被划分成链路分区和路由器分区的多跳通信网络相互连接。 连接分隔件至少部分地实现在用于水平堆叠的模具的插入件的金属层中。 链路分区还可以部分地由单个管芯中的管芯内互连和通过垂直堆叠的管芯组连接的晶片间互连来实现。 路由器分区在设置在插入器处的部分或全部芯片上实现，并且包括支持经由链路分区的互连来在处理系统的组件之间路由分组的功能的逻辑。 路由器分区可以实现固定路由，或者可以使用可编程路由表或可配置逻辑块来配置。

公开(公告)号：US20140181412A1

公开(公告)日：2014-06-26

申请号：US13725011

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh ,  James M. O'Connor ,  Yasuko Eckert ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F12/0848

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括缓存和用于存储器请求的一个或多个源。 响应于接收到分配第一类型的数据的请求，高速缓存控制器响应于确定未达到高速缓存中允许的第一类型的数据量的极限而分配缓存中的数据。 控制器维护存储在高速缓存中的第一类型的数据的量和位置信息。 此外，可以用指定用于存储给定类型的数据的每个分区对高速缓存进行分区。 第一类型的数据的分配至少依赖于第一分区的可用性和第二分区中第一类型的数据量的限制。

公开(公告)号：US09075730B2

公开(公告)日：2015-07-07

申请号：US13725011

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh ,  James M. O'Connor ,  Yasuko Eckert ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0871 ,  G06F12/0848

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括缓存和用于存储器请求的一个或多个源。 响应于接收到分配第一类型的数据的请求，高速缓存控制器响应于确定未达到高速缓存中允许的第一类型的数据量的极限而分配缓存中的数据。 控制器维护存储在高速缓存中的第一类型的数据的量和位置信息。 此外，可以用指定用于存储给定类型的数据的每个分区对高速缓存进行分区。 第一类型的数据的分配至少依赖于第一分区的可用性和第二分区中第一类型的数据量的限制。

公开(公告)号：US20140177626A1

公开(公告)日：2014-06-26

申请号：US13726142

申请日：2012-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: H04L12/56 ,  H01L23/498

CPC classification number: H04L45/021 ,  G06F17/5068 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1461 ,  H01L2924/15192 ,  H04L45/00 ,  H01L2924/00

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

Abstract translation: 电子组件包括设置在插入器处的水平堆叠的管芯，并且还可以包括垂直堆叠的管芯。 堆叠的管芯通过被划分成链路分区和路由器分区的多跳通信网络相互连接。 连接分隔件至少部分地实现在用于水平堆叠的模具的插入件的金属层中。 链路分区还可以部分地由单个管芯中的管芯内互连和通过垂直堆叠的管芯组连接的晶片间互连来实现。 路由器分区在设置在插入器处的部分或全部芯片上实现，并且包括支持通过链路分区的互连来在处理系统的组件之间路由分组的功能的逻辑。 路由器分区可以实现固定路由，或者可以使用可编程路由表或可配置逻辑块来配置。

公开(公告)号：US20140143505A1

公开(公告)日：2014-05-22

申请号：US13736063

申请日：2013-01-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jaewoong Sim ,  Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0888

Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory

Abstract translation: 所描述的实施例包括具有包括模式设置机制的高速缓存控制器的主存储器和高速缓冲存储器（或“高速缓存”）。 在一些实施例中，模式设置机制被配置为动态地确定主存储器的访问模式。 基于确定的访问模式，模式设置机制以回写模式配置主存储器的至少一个区域，并以直通模式配置主存储器的其他区域。 在这些实施例中，当在高速缓冲存储器中执行写入操作时，高速缓存控制器确定高速缓存块所处的主存储器中的区域是否配置在回写模式或直写模式中，然后执行相应的 在高速缓存中写入操作

公开(公告)号：US09825843B2

公开(公告)日：2017-11-21

申请号：US14715023

申请日：2015-05-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: H01L25/065 ,  H01L23/498 ,  H04L12/755 ,  G06F17/50 ,  H01L23/48 ,  H01L23/538 ,  H04L12/701 ,  H01L25/18

CPC classification number: H04L45/021 ,  G06F17/5068 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1461 ,  H01L2924/15192 ,  H04L45/00 ,  H01L2924/00

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

公开(公告)号：US09529718B2

公开(公告)日：2016-12-27

申请号：US14569175

申请日：2014-12-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Syed Ali R. Jafri ,  Yasuko Eckert ,  Srilatha Manne ,  Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/62 ,  Y02D10/13

Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.

Abstract translation: 为了有效地将数据从高速缓存传输到存储器，期望将与存储器中的相同页面相对应的更多数据加载到行缓冲器中。 将数据写入当前未加载到行缓冲区的内存页面时，需要关闭旧页面并打开新页面。 两种操作都消耗能量和时钟周期，并可能延迟更多关键的存储器读取请求。 因此，期望具有多于一个写入同一DRAM页面的写入以分摊打开和关闭DRAM页面的成本。 期望的方法是通过将修改的块保留在高速缓存中来批量回写到相同的DRAM页面，直到属于同一存储器页面的足够数量的修改的块准备好回写。

公开(公告)号：US20160062803A1

公开(公告)日：2016-03-03

申请号：US14935056

申请日：2015-11-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/50 ,  G06F12/08

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.

Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制在从一组表中选择的表中执行查找以从资源集合中识别资源。 当资源不可用于执行操作并且直到选择用于执行操作的另一资源为止时，选择机制识别表中的下一个资源，并且当下一个资源可用于执行操作时选择用于执行操作的下一个资源 。

公开(公告)号：US09183055B2

公开(公告)日：2015-11-10

申请号：US13761985

申请日：2013-02-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.

Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制被配置为在从一组表中选择的表中执行查找，以从资源集合中识别资源。 当所识别的资源不可用于执行操作并且直到选择资源来执行操作时，选择机制被配置为识别表中的下一个资源，并且当下一个资源可用时选择用于执行操作的下一个资源 用于执行操作。