公开(公告)号：US12176065B2

公开(公告)日：2024-12-24

申请号：US17849197

申请日：2022-06-24

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Xuan Chen ,  Chih-Hua Hsu ,  Pradeep Jayaraman ,  Abdussalam Aburwein

IPC: G11C7/22 ,  G11C5/02 ,  G11C7/10 ,  G11C8/18

Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.

公开(公告)号：US11960435B2

公开(公告)日：2024-04-16

申请号：US17692147

申请日：2022-03-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Pradeep Jayaraman ,  Dean Gonzales ,  Gerald R. Talbot ,  Ramon A. Mangaser ,  Michael J. Tresidder ,  Prasant Kumar Vallur ,  Srikanth Reddy Gruddanti ,  Krishna Reddy Mudimela Venkata ,  David H. McIntyre

IPC: G06F13/42 ,  H01L25/065

CPC classification number: G06F13/4291 ,  G06F13/4286 ,  H01L25/0652

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

公开(公告)号：US20240112720A1

公开(公告)日：2024-04-04

申请号：US17957788

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D Willey ,  Karthik Gopalakrishnan ,  Pradeep Jayaraman

IPC: G11C11/4076

CPC classification number: G11C11/4076

Abstract: A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory, a first group of driver circuits providing CA signals to the memory, and a second group of driver circuits providing DQ signals to the memory. A plurality of the conductive traces which carry the DQ signals are constructed with a length longer than that of conductive traces carrying the reference clock signal in order to reduce an effective insertion delay associated with coupling the reference clock signal to latch respective incoming DQ signals.

公开(公告)号：US20230046477A1

公开(公告)日：2023-02-16

申请号：US17545108

申请日：2021-12-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Ramon Mangaser ,  Karthik Gopalakrishnan ,  Andy Huei Chu ,  Pradeep Jayaraman

IPC: H04B3/56 ,  G05F1/46 ,  H04B3/06

Abstract: A data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit. The first circuit includes a transmitter powered by a first power supply voltage and having an input for receiving a data output signal, and an output. The second circuit includes a receiver powered by a second power supply voltage and having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage.

公开(公告)号：US20220038102A1

公开(公告)日：2022-02-03

申请号：US17502741

申请日：2021-10-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Achal Kathuria ,  Pradeep Jayaraman

IPC: H03K21/08 ,  H03K5/24 ,  H03K19/01

Abstract: Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

公开(公告)号：US20210083677A1

公开(公告)日：2021-03-18

申请号：US16570334

申请日：2019-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Achal Kathuria ,  Pradeep Jayaraman

IPC: H03K21/08 ,  H03K19/01 ,  H03K5/24

Abstract: Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

公开(公告)号：US12154656B2

公开(公告)日：2024-11-26

申请号：US17854213

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D Willey ,  Karthik Gopalakrishnan ,  Pradeep Jayaraman

IPC: G11C7/14 ,  G11C7/10 ,  G11C29/52

Abstract: A receiver is trained for receiving a signal over a data bus. A volatile memory is commanded over the data bus to place a selected pulse-amplitude modulation (PAM) driver in a mode with a designated steady output level. At a receiver circuit coupled to the selected PAM driver, a respective reference voltage associated with the designated steady output level is swept through a range of voltages and the respective reference voltage is compared to a voltage received from the PAM driver to determine a respective voltage level received from the PAM driver.

公开(公告)号：US20240214246A1

公开(公告)日：2024-06-27

申请号：US18086960

申请日：2022-12-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Pradeep Jayaraman ,  Karthik Gopalakrishnan ,  Andrew Egli

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/03038 ,  H04L25/4917 ,  H04L2025/03471

Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.

公开(公告)号：US12015412B1

公开(公告)日：2024-06-18

申请号：US18060857

申请日：2022-12-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Srikanth Reddy Gruddanti ,  Pradeep Jayaraman ,  Ramon A. Mangaser ,  Prasant Kumar Vallur ,  Krishna Reddy Mudimela Venkata ,  David H. McIntyre

IPC: H03K5/24 ,  H03K5/14 ,  H03L7/099 ,  H03K5/00

CPC classification number: H03K5/249 ,  H03K5/14 ,  H03L7/0998 ,  H03K2005/00286

Abstract: A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.

公开(公告)号：US20240192858A1

公开(公告)日：2024-06-13

申请号：US18079239

申请日：2022-12-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron D. Willey ,  Karthik Gopalakrishnan ,  Pradeep Jayaraman

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0673

Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.