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    Package substrate, electronic device package and method for manufacturing the same
    15.
    发明授权
    Package substrate, electronic device package and method for manufacturing the same 有权

    公开(公告)号：US11335650B2

    公开(公告)日：2022-05-17

    申请号：US16899515

    申请日：2020-06-11

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Wu Chou Hsu ,  Chih-Cheng Lee ,  Min-Yao Chen ,  Hsing Kuo Tien

    IPC: H01L23/64 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.

    SEMICONDUCTOR PACKAGE STRUCTURE
    16.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权

    公开(公告)号：US20210391291A1

    公开(公告)日：2021-12-16

    申请号：US16898064

    申请日：2020-06-10

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chih-Cheng Lee ,  Jiming Li

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48

    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure includes a substrate, a chip and a dielectric structure. The substrate includes a first portion and a second portion surrounding the first portion. The second portion defines a cavity over the first portion. The chip includes a terminal on an upper surface of the chip. The dielectric structure fills the cavity and laterally encroaches over the upper surface of the chip. The dielectric structure is free from overlapping with the terminal of the chip.

    Substrate structure having pad portions
    17.
    发明授权
    Substrate structure having pad portions 有权

    公开(公告)号：US11101186B2

    公开(公告)日：2021-08-24

    申请号：US16297451

    申请日：2019-03-08

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

    IPC: H01L27/32 ,  H01L23/31 ,  H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A substrate structure includes a wiring structure and a supporter. The wiring structure includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is disposed on the first dielectric structure. The second dielectric structure covers the first dielectric structure and the first circuit layer. A pad portion of the first circuit layer is exposed from the first dielectric structure, and the second circuit layer protrudes from the second dielectric structure. The supporter is disposed adjacent to the first dielectric structure of the wiring structure, and defines at least one through hole corresponding to the exposed pad portion of the first circuit layer.

    Substrate, semiconductor device package and method of manufacturing the same
    18.
    发明授权
    Substrate, semiconductor device package and method of manufacturing the same 有权

    公开(公告)号：US11088061B2

    公开(公告)日：2021-08-10

    申请号：US16814729

    申请日：2020-03-10

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

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