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11.发明授权公开(公告)号：US11348643B2
公开(公告)日：2022-05-31
申请号：US16799874
申请日：2020-02-25
Applicant: Apple Inc.
Inventor： Itay Sagron , Assaf Shappir
Abstract: A controller includes an interface and storage circuitry. The interface is configured to communicate with a memory device that includes multiple memory cells organized in memory blocks. The memory device supporting programming of the memory cells with enabled or disabled program-verification. The storage circuitry is configured to disable the program-verification, and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse, to read the data from the group of the memory cells. In response to detecting a failure in reading the data, the storage circuitry is configured to distinguish between whether the memory cells in the group belong to a defective memory block or were under-programmed, and when identifying that the memory cells in the group were under-programmed, to perform a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.
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公开(公告)号：US10762967B2
公开(公告)日：2020-09-01
申请号：US16202130
申请日：2018-11-28
Applicant: Apple Inc.
Inventor： Assaf Shappir , Barak Baum , Itay Sagron , Roman Guy , Guy Ben-Yehuda , Stas Mouler
Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.
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公开(公告)号：US10755787B2
公开(公告)日：2020-08-25
申请号：US16202127
申请日：2018-11-28
Applicant: Apple Inc.
Inventor： Eli Yazovitsky , Assaf Shappir , Itay Sagron , Meir Dalal
Abstract: A storage device includes storage circuitry and multiple memory cells. The memory cells are organized in multiple memory blocks of a nonvolatile memory. The storage circuitry is configured to define a partial verification scheme that specifies testing only a data portion of the data programmed to the memory blocks, to program data to a memory block, calculate redundancy data over the data, and save the calculated redundancy data in a dedicated memory, to verify that the data portion specified for the memory block in the partial verification scheme has been programmed successfully, to check a predefined condition for conditionally performing full verification to the memory block, when the predefined condition is fulfilled, to verify that data programmed to the memory block and not tested using the partial verification scheme has been programmed successfully, and to recover, using the redundancy data, at least part of the data programmed that failed verification.
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公开(公告)号：US10475524B2
公开(公告)日：2019-11-12
申请号：US15265869
申请日：2016-09-15
Applicant: Apple Inc.
Inventor： Assaf Shappir , Eyal Gurgi
Abstract: A memory controller includes an interface and circuitry. The interface is configured to communicate with a memory device, which includes multiple memory cells, and which applies refreshing to the memory cells by repeatedly inverting data stored in the memory cells. The circuitry is configured to store input data in a group of the memory cells, to read the stored input data from the group of the memory cells to produce read data, the read data has an actual polarity that is either un-inverted or inverted due to the refreshing of the memory cells in the group, to analyze the read data for identifying the actual polarity of the read data, and to recover the input data from the read data based on the identified actual polarity.
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公开(公告)号：US20180181500A1
公开(公告)日：2018-06-28
申请号：US15387699
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Assaf Shappir , Itay Sagron
CPC classification number: G06F21/602 , G06F21/60 , G06F21/6245 , G06F21/75 , G06F21/79 , G06F21/86 , G11C7/24 , G11C11/5635 , G11C11/5642 , G11C16/22 , G11C29/50 , G11C2029/4402 , G11C2029/5002
Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level.
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Patent Agency Ranking
公开(公告)号：US20170147730A1
公开(公告)日：2017-05-25
申请号：US14948407
申请日：2015-11-23
Applicant: Apple Inc.
Inventor： Assaf Shappir
IPC: G06F17/50 , H01L27/115
CPC classification number: G06F17/5068 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11582
Abstract: A method for designing a patterning process for a three-dimensional (3D) memory includes defining a target 3D structure of the 3D memory, to be applied in a periodic structure of layers on a substrate. The target 3D structure is converted into a sequence of multiple steps, each step specifying a respective pattern to be removed and a respective number of the layers to be removed from the periodic structure under the respective pattern. The sequence of steps is sent to one or more manufacturing tools.
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17.发明授权公开(公告)号：US10936456B1
公开(公告)日：2021-03-02
申请号：US16280090
申请日：2019-02-20
Applicant: Apple Inc.
Inventor： Yael Shur , Assaf Shappir , Stas Mouler , Yoav Kasorla
Abstract: A controller includes an interface and storage circuitry. The interface communicates with one or more memory devices, each of the memory devices includes multiple memory cells organized in memory blocks. The storage circuitry is configured to perform multiple storage operations to the memory cells in the one or more memory devices, and mark memory blocks in which one or more storage operations have failed as bad blocks. The controller is further configured to identify a pattern of multiple bad blocks occurring over a sequence of multiple consecutive storage operations, the pattern is indicative of a system-level malfunction in a memory system including the controller, and in response to identifying the pattern, to perform a corrective action to the memory system.
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公开(公告)号：US10740476B2
公开(公告)日：2020-08-11
申请号：US16379817
申请日：2019-04-10
Applicant: Apple Inc.
Inventor： Assaf Shappir , Itay Sagron
IPC: G06F21/60 , G11C11/56 , G06F21/86 , G06F21/75 , G06F21/62 , G06F21/79 , G11C7/24 , G11C16/22 , G11C29/50 , G11C29/44
Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level.
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公开(公告)号：US20200005874A1
公开(公告)日：2020-01-02
申请号：US16202130
申请日：2018-11-28
Applicant: Apple Inc.
Inventor： Assaf Shappir , Barak Baum , Itay Sagron , Roman Guy , Guy Ben-Yehuda , Stas Mouler
Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.
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公开(公告)号：US20190236288A1
公开(公告)日：2019-08-01
申请号：US16379817
申请日：2019-04-10
Applicant: Apple Inc.
Inventor： Assaf Shappir , Itay Sagron
IPC: G06F21/60 , G06F21/79 , G06F21/86 , G11C29/50 , G11C16/22 , G11C7/24 , G11C11/56 , G06F21/62 , G06F21/75
CPC classification number: G06F21/602 , G06F21/60 , G06F21/6245 , G06F21/75 , G06F21/79 , G06F21/86 , G11C7/24 , G11C11/5635 , G11C11/5642 , G11C16/22 , G11C29/50 , G11C2029/4402 , G11C2029/5002
Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level.
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