公开(公告)号：US20180292885A1

公开(公告)日：2018-10-11

申请号：US15942230

申请日：2018-03-30

Applicant: APPLE INC.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US09971397B2

公开(公告)日：2018-05-15

申请号：US14879027

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F1/32 ,  G06F13/42 ,  G06F9/44 ,  G06F11/14

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20170286323A1

公开(公告)日：2017-10-05

申请号：US15271109

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F21/62

CPC classification number: G06F12/1441 ,  G06F12/1081 ,  G06F2212/1052

Abstract: Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.

公开(公告)号：US09621245B2

公开(公告)日：2017-04-11

申请号：US14577834

申请日：2014-12-19

Applicant: Apple Inc.

Inventor： Ming Hu ,  Haining Zhang ,  Xueting Liu

IPC: H03C7/02 ,  H04B7/06 ,  H04B1/3827 ,  H01Q1/24 ,  H01Q21/28 ,  H04B17/11 ,  H01Q3/24 ,  H04B7/00

CPC classification number: H04B7/0602 ,  H01Q1/243 ,  H01Q3/24 ,  H01Q21/28 ,  H04B1/3838 ,  H04B7/0608 ,  H04B17/11

Abstract: The disclosed embodiments provide a system that uses a first antenna and a second antenna in a portable electronic device. During operation, the system receives a request to switch from the first antenna to the second antenna to transmit a signal to a cellular receiver. Next, the system loads a set of radio-frequency (RF) calibration values for the second antenna. Finally, the system performs the switch from the first antenna to the second antenna to transmit the signal, wherein the second antenna is operated using the RF calibration values after the switch.

公开(公告)号：US20160103480A1

公开(公告)日：2016-04-14

申请号：US14879027

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

Abstract translation: 两个（或多个）可独立操作的处理器之间的处理器间通信（IPC）链接的方法和装置。 在一个方面，IPC协议基于用于运行时处理的“共享”存储器接口（即，独立可操作的处理器每个共享（虚拟或物理上）公共存储器接口）。 在另一方面，IPC通信链路被配置为支持在引导序列期间使用的主机驱动的引导协议，以在外围设备和主处理器之间建立基本通信路径。 本文描述的各种其他实施例包括睡眠过程（如针对主机和外围处理器分别定义的）和错误处理。

公开(公告)号：US20150188616A1

公开(公告)日：2015-07-02

申请号：US14577834

申请日：2014-12-19

Applicant: Apple Inc.

Inventor： Ming Hu ,  Haining Zhang ,  Xueting Liu

IPC: H04B7/06 ,  H01Q21/28 ,  H01Q3/24

CPC classification number: H04B7/0602 ,  H01Q1/243 ,  H01Q3/24 ,  H01Q21/28 ,  H04B1/3838 ,  H04B7/0608 ,  H04B17/11

Abstract: The disclosed embodiments provide a system that uses a first antenna and a second antenna in a portable electronic device. During operation, the system receives a request to switch from the first antenna to the second antenna to transmit a signal to a cellular receiver. Next, the system loads a set of radio-frequency (RF) calibration values for the second antenna. Finally, the system performs the switch from the first antenna to the second antenna to transmit the signal, wherein the second antenna is operated using the RF calibration values after the switch.

Abstract translation: 所公开的实施例提供了在便携式电子设备中使用第一天线和第二天线的系统。 在操作期间，系统接收从第一天线切换到第二天线的请求，以将信号发送到蜂窝接收机。 接下来，系统为第二天线加载一组射频（RF）校准值。 最后，系统执行从第一天线到第二天线的切换以发送信号，其中使用切换后的RF校准值来操作第二天线。

公开(公告)号：US10572390B2

公开(公告)日：2020-02-25

申请号：US15273413

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F12/1009 ,  G06F8/61 ,  G06F13/42 ,  G06F1/24 ,  G06F12/14 ,  G06F3/06

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US20190317591A1

公开(公告)日：2019-10-17

申请号：US16390998

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F1/3293 ,  G06F13/42 ,  G06F1/3287 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20190227944A1

公开(公告)日：2019-07-25

申请号：US16259957

申请日：2019-01-28

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/14 ,  G06F8/61 ,  G06F1/24 ,  G06F13/42

Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

公开(公告)号：US20190132797A1

公开(公告)日：2019-05-02

申请号：US16140317

申请日：2018-09-24

Applicant: APPLE INC.

Inventor： Richard M. Solotke ,  Saurabh Garg ,  Haining Zhang

IPC: H04W52/02

Abstract: Methods and apparatus for limiting wake requests from one device to one or more other devices. In one embodiment, the requests are from a peripheral processor to a host processor within an electronic device such as a mobile smartphone or tablet which has power consumption requirements or considerations associated therewith. In one implementation, the peripheral processor includes a wake-limiting procedure encoded in e.g., its software or firmware, the procedure mitigating or preventing continuous and/or overly repetitive “wake” requests from the peripheral processor.