公开(公告)号：US20240428502A1

公开(公告)日：2024-12-26

申请号：US18653567

申请日：2024-05-02

Applicant: Apple Inc.

Inventor： Fu-Chung Huang ,  ByoungSuk Kim ,  Felipe Bacim De Araujo E Silva ,  Hao Chen ,  Igor Kozintsev ,  Pavel V Dudrenov ,  Ping-Yen Chou ,  Seung Wook Kim ,  Sheng Zhang ,  Victor H Yin ,  Wei H Yao ,  Wei Xiong ,  Yang Li ,  Yi Huang ,  Yi-Pai Huang ,  Justin A Meiners

IPC: G06T15/06 ,  H04N13/133 ,  H04N13/305

Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. The lenticular lenses may be configured to enable stereoscopic viewing of the display such that a viewer perceives three-dimensional images. The display may render different content layers that present different classes of content. The different classes of content may have different characteristics. As an example, a first class of content may be static content whereas a second class of content may be dynamic content. The different characteristics of each class of content may be leveraged to use a hybrid approach for content processing. The hybrid content processing may take advantage of different layers needing to be updated at different frequencies and may take advantage of sparse content in some of the layers.

公开(公告)号：US20200341533A1

公开(公告)日：2020-10-29

申请号：US16397888

申请日：2019-04-29

Applicant: Apple Inc.

Inventor： Ching Elizabeth Ho ,  Hao Chen ,  Nitin Bhargava ,  Syed F. Ali

IPC: G06F1/329 ,  G06F1/3228

Abstract: An apparatus includes a plurality of processor cores, a cache memory that includes a plurality of banks, and a power management circuit. The power management circuit is configured to maintain a power credit approach for the apparatus that includes tracking a total number of currently available power credits, and to store a plurality of threshold values. Each threshold value is associated with one or more of a plurality of throttling actions. In response to the total number of currently available power credits reaching a particular threshold value of the plurality of threshold values, the power management circuit performs the one or more throttling actions associated with the particular threshold value. The plurality of throttling actions includes selectively throttling one or more of the plurality of processor cores, and selectively throttling one or more of the plurality of banks in the cache memory.

公开(公告)号：US20150302544A1

公开(公告)日：2015-10-22

申请号：US14258662

申请日：2014-04-22

Applicant: Apple Inc.

Inventor： Hao Chen ,  Benjamin K. Dodge ,  Peter F. Holland

IPC: G06T1/20

CPC classification number: G09G5/397 ,  G09G5/001 ,  G09G5/14 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2350/00 ,  G09G2352/00 ,  G09G2360/125

Abstract: Systems and methods for determining priorities of pixel fetch requests of separate requestors in a display control unit. The distance between the oldest pixel in an output buffer and the output equivalent coordinate of the oldest outstanding source pixel read request for each requestor in the display control unit is calculated. Then, a priority is assigned to each requestor based on this calculated distance. If a given requestor lags behind the other requestors based on a comparison of the distance between the oldest pixel and the output equivalent coordinate of the oldest outstanding source pixel read, then source pixel fetch requests for this given requestor are given a higher priority than source pixel fetch requests for the other requestors.

Abstract translation: 用于确定显示控制单元中单独请求者的像素提取请求的优先级的系统和方法。 计算输出缓冲器中的最旧像素与显示控制单元中每个请求者的最早未完成源像素读取请求的输出等效坐标之间的距离。 然后，基于该计算出的距离将优先级分配给每个请求者。 如果给定的请求者基于最旧的像素读取的最旧的源像素的输出等效坐标之间的距离的比较而落在其他请求者之后，则给予该给定请求者的源像素提取请求被给予比源像素更高的优先级 提取其他请求者的请求。

公开(公告)号：US09105112B2

公开(公告)日：2015-08-11

申请号：US13773522

申请日：2013-02-21

Applicant: Apple Inc.

Inventor： Peter Holland ,  Hao Chen ,  Albert Kuo

IPC: G06T3/40 ,  G06T1/60 ,  G06F1/32

CPC classification number: G06T1/60 ,  G06F1/3228 ,  G06F1/3265 ,  G06F1/3287 ,  G06T3/4007 ,  G09G5/363 ,  G09G5/391 ,  G09G5/395 ,  G09G5/399 ,  G09G2330/021 ,  G09G2340/0407 ,  G09G2340/045 ,  G09G2360/127 ,  Y02D10/153 ,  Y02D10/171 ,  Y02D50/20

Abstract: Techniques are disclosed relating to power management within an integrated circuit. In one embodiment, a display buffer receives image data through a data transfer interconnect. A data transfer interconnect is powered down based on the received image data being greater than a threshold amount of data. The display buffer transmits at least a portion of the image data to one or more outputs, and in response to the transmitting, the data transfer interconnect is powered up. In some embodiments, the display buffer includes a plurality of line buffers, each configured to store a respective image source line. In such an embodiment, a display pipe configured to render images to be displayed includes the display buffer, and the powering down is performed in response to the received image data including two or more image source lines.

Abstract translation: 公开了与集成电路内的电源管理有关的技术。 在一个实施例中，显示缓冲器通过数据传输互连接收图像数据。 基于接收到的图像数据大于阈值数据量，数据传输互连被断电。 显示缓冲器将图像数据的至少一部分发送到一个或多个输出，并且响应于发送，数据传输互连被加电。 在一些实施例中，显示缓冲器包括多个行缓冲器，每个行缓冲器被配置为存储相应的图像源线。 在这样的实施例中，被配置为使得要显示的图像的显示管道包括显示缓冲器，并且响应于包括两个或更多个图像源线的接收图像数据执行掉电。

公开(公告)号：US20150062134A1

公开(公告)日：2015-03-05

申请号：US14017742

申请日：2013-09-04

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Brijesh Tripathi ,  Hao Chen

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G09G5/00 ,  G06F5/10 ,  G09G5/363 ,  H04N5/00 ,  H04N5/14 ,  H04N7/025 ,  H04N7/0884

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve a top frame packet from the parameter buffer and determine if the frame packet is an internal type, i.e., intended for internal registers in a respective processing unit or if it is an external type, i.e., intended for an external register elsewhere in the graphics system. Based on the type of frame packet, the control circuit may update one or more register values accordingly.

Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索顶部帧分组，并且确定帧分组是否是内部类型，即针对相应处理单元中的内部寄存器，或者如果它 是一种外部类型，即用于图形系统中其他地方的外部寄存器。 基于帧分组的类型，控制电路可以相应地更新一个或多个寄存器值。

公开(公告)号：US20140052937A1

公开(公告)日：2014-02-20

申请号：US14062302

申请日：2013-10-24

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Hao Chen ,  Ruchi Wadhawan

IPC: G06F13/16

CPC classification number: G06F13/1694 ,  G06F13/1684

Abstract: In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Abstract translation: 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

公开(公告)号：US12200185B1

公开(公告)日：2025-01-14

申请号：US17885455

申请日：2022-08-10

Applicant: Apple Inc.

Inventor： Felipe Bacim De Araujo E Silva ,  Seung Wook Kim ,  Edwin Iskandar ,  Pavel V Dudrenov ,  Zachary D Corley ,  Hao Chen ,  Ping-Yen Chou

IPC: H04N13/305 ,  H04N13/15 ,  H04N13/167 ,  H04N13/327 ,  H04N13/398 ,  H04N13/366

Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. The display may include ray tracing circuitry that is configured to, using ray tracing, a three-dimensional image, and deflection measurements for the array of pixels, output a display calibration map that includes, for each pixel in the array of pixels, a corresponding location on a two-dimensional image. The display may also include pixel mapping circuitry configured to, using the display calibration map from the ray tracing circuitry, map the two-dimensional image to respective pixels on the array of pixels to obtain pixel data for the array of pixels.

公开(公告)号：US20240348767A1

公开(公告)日：2024-10-17

申请号：US18432303

申请日：2024-02-05

Applicant: Apple Inc.

Inventor： Ping-Yen Chou ,  ByoungSuk Kim ,  Cheng-Ho Yu ,  Fu-Chung Huang ,  Hao Chen ,  Juan He ,  Jun Qi ,  Manjap Singh ,  Xiaofeng Wang ,  Yang Li ,  Yi Huang ,  Yi-Pai Huang

IPC: H04N13/305 ,  H04N13/324 ,  H04N13/351

CPC classification number: H04N13/305 ,  H04N13/324 ,  H04N13/351

Abstract: A display may include an array of pixels covered by lenticular lenses. The lenticular lenses may cause expansion of light primarily in a horizontal direction. To improve the perceived resolution of the display, the horizontal resolution of the pixels on the display may be increased. In one possible layout, each pixel includes one red sub-pixel, one blue sub-pixel, and one green sub-pixel. The sub-pixels may be non-square rectangular. The sub-pixels may be the same size or may have the same widths and different heights. Each pixel may be asymmetric about a horizontal axis. In a given row, the pixels may alternate between first and second layouts. The second layout may be a vertically flipped version of the first layout.

公开(公告)号：US09747658B2

公开(公告)日：2017-08-29

申请号：US14019909

申请日：2013-09-06

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Albert C. Kuo ,  Hao Chen

IPC: G06T1/20

CPC classification number: G06T1/20

Abstract: Embodiments of an apparatus and method are disclosed that may allow for arbitrating multiple read requests to fetch pixel data from a memory. The apparatus may include a first and a second processing pipeline, and a control unit. Each of the processing pipelines may be configured to generate a plurality of read requests to fetch a respective one of a plurality of portions of stored pixel data. The control unit may be configured to determine a priority for each read request dependent upon display coordinates of one or more pixels corresponding to each of the plurality of portions of stored pixel data, and determine an order for the plurality of read requests dependent upon the determined priority for each read request.

公开(公告)号：US09454378B2

公开(公告)日：2016-09-27

申请号：US14083010

申请日：2013-11-18

Applicant: Apple Inc.

Inventor： Guy Cote ,  Joseph P. Bratt ,  Nitin Bhargava ,  Hao Chen ,  Joseph J. Cheng

IPC: G06F3/00 ,  G06F13/00 ,  G06F9/44 ,  G06F3/06 ,  G06F9/445

CPC classification number: G06F9/4401 ,  G06F3/0629 ,  G06F8/71 ,  G06F9/445

Abstract: Methods and apparatus for configuring multiple components of a subsystem are described. The configuration memory of each of a plurality of components coupled to an interconnect includes a global configuration portion. The configuration memory of one of the components may be designated as a master global configuration for all of the components. A module coupled to the interconnect may receive writes to the components from a configuration source. For each write, the module may decode the write to determine addressing information and check to see if the write is addressed to the master global configuration. If the write is addressed to the master global configuration, the module broadcasts the write to the global configuration portion of each of the components via the interconnect. If the write is not addressed to the master global configuration, the module forwards the write to the appropriate component via the interconnect.

Abstract translation: 描述用于配置子系统的多个组件的方法和装置。 耦合到互连的多个组件中的每一个的配置存储器包括全局配置部分。 可以将组件之一的配置存储器指定为用于所有组件的主全局配置。 耦合到互连的模块可以从配置源接收对组件的写入。 对于每次写入，模块可以解码写入以确定寻址信息，并检查写入是否寻址到主全局配置。 如果写入寻址到主全局配置，则模块通过互连广播写入每个组件的全局配置部分。 如果写入不适用于主全局配置，则模块通过互连将写入转发到相应的组件。