公开(公告)号：US11550657B1

公开(公告)日：2023-01-10

申请号：US17463612

申请日：2021-09-01

Applicant: APPLE INC.

Inventor： Assaf Shappir ,  Itay Sagron

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/56

Abstract: A storage apparatus includes an interface and storage circuitry. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple programming levels. The storage circuitry configured to program data to a first group of multiple memory cells in a number of programming levels larger than two, using a One-Pass Programming (OPP) scheme that results in a first readout reliability level. After programming the data, the storage circuitry is further configured to read the data from the first group, and program the data read from the first group to a second group of the memory cells, in a number of programming levels larger than two, using a Multi-Pass Programming (MPP) scheme that results in a second readout reliability higher than the first reliability level, and reading the data from the second group of the memory cells.

公开(公告)号：US11348643B2

公开(公告)日：2022-05-31

申请号：US16799874

申请日：2020-02-25

Applicant: Apple Inc.

Inventor： Itay Sagron ,  Assaf Shappir

IPC: G11C16/34 ,  G11C16/10 ,  G06F11/10 ,  G11C16/26 ,  G11C16/04

Abstract: A controller includes an interface and storage circuitry. The interface is configured to communicate with a memory device that includes multiple memory cells organized in memory blocks. The memory device supporting programming of the memory cells with enabled or disabled program-verification. The storage circuitry is configured to disable the program-verification, and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse, to read the data from the group of the memory cells. In response to detecting a failure in reading the data, the storage circuitry is configured to distinguish between whether the memory cells in the group belong to a defective memory block or were under-programmed, and when identifying that the memory cells in the group were under-programmed, to perform a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.

公开(公告)号：US10762967B2

公开(公告)日：2020-09-01

申请号：US16202130

申请日：2018-11-28

Applicant: Apple Inc.

Inventor： Assaf Shappir ,  Barak Baum ,  Itay Sagron ,  Roman Guy ,  Guy Ben-Yehuda ,  Stas Mouler

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G06F11/10 ,  G11C29/12

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.

公开(公告)号：US10755787B2

公开(公告)日：2020-08-25

申请号：US16202127

申请日：2018-11-28

Applicant: Apple Inc.

Inventor： Eli Yazovitsky ,  Assaf Shappir ,  Itay Sagron ,  Meir Dalal

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C29/52 ,  G06F11/10 ,  G11C29/12

Abstract: A storage device includes storage circuitry and multiple memory cells. The memory cells are organized in multiple memory blocks of a nonvolatile memory. The storage circuitry is configured to define a partial verification scheme that specifies testing only a data portion of the data programmed to the memory blocks, to program data to a memory block, calculate redundancy data over the data, and save the calculated redundancy data in a dedicated memory, to verify that the data portion specified for the memory block in the partial verification scheme has been programmed successfully, to check a predefined condition for conditionally performing full verification to the memory block, when the predefined condition is fulfilled, to verify that data programmed to the memory block and not tested using the partial verification scheme has been programmed successfully, and to recover, using the redundancy data, at least part of the data programmed that failed verification.

公开(公告)号：US20180181500A1

公开(公告)日：2018-06-28

申请号：US15387699

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Assaf Shappir ,  Itay Sagron

IPC: G06F12/14 ,  G11C11/56 ,  G06F3/06

CPC classification number: G06F21/602 ,  G06F21/60 ,  G06F21/6245 ,  G06F21/75 ,  G06F21/79 ,  G06F21/86 ,  G11C7/24 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/22 ,  G11C29/50 ,  G11C2029/4402 ,  G11C2029/5002

Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level.

公开(公告)号：US09817595B2

公开(公告)日：2017-11-14

申请号：US15008470

申请日：2016-01-28

Applicant: APPLE INC.

Inventor： Barak Rotbard ,  Itay Sagron

IPC: G06F13/00 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/064 ,  G06F3/0673 ,  G11C16/30

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that include multiple memory blocks. The processor is configured to hold information regarding power consumption of the memory blocks, to group at least some of the memory blocks into one or more storage groups, based on the information, such that the memory blocks in each storage group jointly consume less than a predefined power limit when the memory blocks in the storage group are applied a storage operation in parallel, and to apply the storage operation, in parallel, to the memory blocks in a selected storage group.