公开(公告)号：US10049073B2

公开(公告)日：2018-08-14

申请号：US15621265

申请日：2017-06-13

Applicant: Apple Inc.

Inventor： Michael J. Smith ,  Josh P. de Cesare ,  Brijesh Tripathi ,  Derek Iwamoto ,  Shane J Keil

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  G06F13/10 ,  G06F13/28

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

公开(公告)号：US20170277648A1

公开(公告)日：2017-09-28

申请号：US15621265

申请日：2017-06-13

Applicant: Apple Inc.

Inventor： Michael J. Smith ,  Josh P. de Cesare ,  Brijesh Tripathi ,  Derek Iwamoto ,  Shane J. Keil

IPC: G06F13/42 ,  G06F13/10 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4226 ,  G06F13/105 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

公开(公告)号：US20150356050A1

公开(公告)日：2015-12-10

申请号：US14459731

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Michael J. Smith ,  Josh P. de Cesare ,  Brijesh Tripathi ,  Derek Iwamoto ,  Shane J. Keil

IPC: G06F13/42 ,  G06F13/10 ,  G06F13/40

CPC classification number: G06F13/4226 ,  G06F13/105 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

Abstract translation: 公开了一种用于IC的接口仿真器。 接口仿真器包括第一先入先出存储器（FIFO）和第二FIFO。 第一FIFO被耦合以从接入端口接收数据，并且第二FIFO被耦合以从IC中的至少一个功能单元接收数据。 访问端口可以耦合到IC外部的设备。 外部设备可以将信息写入第一FIFO，并且该信息随后可以由IC中的功能单元读取。 类似地，功能单元可以将信息写入第二FIFO，随后外部设备读取信息。 可以根据预定义的协议将信息写入FIFO。 因此，即使在IC中没有实现用于该接口的物理连接和支持电路，也可以模拟特定类型的接口。

公开(公告)号：US20140122908A1

公开(公告)日：2014-05-01

申请号：US14149922

申请日：2014-01-08

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Jung Wook Cho ,  Toshinari Takayanagi ,  Timothy J. Millet

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

公开(公告)号：US11068419B1

公开(公告)日：2021-07-20

申请号：US16786633

申请日：2020-02-10

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Wade Benson ,  Fabrice L. Gautier ,  Kaiehu Kaahaaina

IPC: G06F12/14 ,  G06F21/62 ,  G06F21/60

Abstract: Techniques are disclosed concerning secure access to data in a computing device. In one embodiment, a computing device includes a communication interface, a memory, a memory controller, and a security processor. The communication interface may communicate with a different computing device. The security processor may generate a host key in response to a successful authentication of the different computing device, and then encrypt a memory key using the host key. The security processor may also send the encrypted memory key to the memory controller, and send the host key to the different computing device. The host key may be included by the different computing device in a subsequent memory request to access data in the memory. The memory controller may, in response to the subsequent memory request, use the included host key to decrypt the encrypted memory key and use the decrypted memory key to access the data.

公开(公告)号：US09703748B2

公开(公告)日：2017-07-11

申请号：US14459731

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Michael J. Smith ,  Josh P. de Cesare ,  Brijesh Tripathi ,  Derek Iwamoto ,  Shane J Keil

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/40 ,  G06F13/10 ,  G06F13/38

CPC classification number: G06F13/4226 ,  G06F13/105 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

公开(公告)号：US09262353B2

公开(公告)日：2016-02-16

申请号：US14590203

申请日：2015-01-06

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Ruchi Wadhawan ,  Erik P. Machnicki ,  Mark D. Hayter

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2424 ,  Y02D10/14

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

公开(公告)号：US20140208135A1

公开(公告)日：2014-07-24

申请号：US13745731

申请日：2013-01-18

Applicant: APPLE INC.

Inventor： Shane J. Keil ,  Erik P. Machnicki ,  Josh P. de Cesare

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

Abstract translation: 公开了与集成电路内的电力管理有关的技术。 在一个实施例中，公开了一种包括电路和电源管理单元的装置。 功率管理单元被配置为基于可编程设置来提供是否允许对电路的尝试通信是使电路退出功率管理状态的指示。 在一些实施例中，该装置包括被配置成从设备将尝试的通信传送到电路的结构。 在这样的实施例中，电路被配置为响应于接收到尝试的通信而退出功率管理状态。 结构被配置为基于由电力管理单元提供的指示来确定是否发送尝试的通信。

公开(公告)号：US20140089712A1

公开(公告)日：2014-03-27

申请号：US13626522

申请日：2012-09-25

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Manu Gulati ,  Josh P. de Cesare

IPC: G06F21/02 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/575 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/74

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包装密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。

公开(公告)号：US20250093925A1

公开(公告)日：2025-03-20

申请号：US18540723

申请日：2023-12-14

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  John H. Kelm ,  Josh P. de Cesare ,  Karl D. Wulcan ,  Michael Bekerman

IPC: G06F1/26

Abstract: An apparatus includes a control circuit, configured to transition a plurality of power domains into selected performance states, and a set of state request registers. A state request register may include fields that are associated with respective power domains. The apparatus may further include circuit blocks configured to store respective state request values into respective state request registers. A given state request value may indicate a requested performance state for at least one of the power domains. In addition, a performance management circuit may be configured to select, using the associated fields in the registers, a particular performance state for at least one of the power domains. The performance management circuit may be further configured to determine a transition path to sequence to the selected performance state, and to cause the control circuit to transition to the selected performance state using the transition path.