公开(公告)号：US20160077989A1

公开(公告)日：2016-03-17

申请号：US14856283

申请日：2015-09-16

Applicant: Apple Inc.

Inventor： Radha Kumar Pulyala ,  Saurabh Garg ,  Karan Sanghi

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/287 ,  G06F13/4022 ,  G06F13/4282

Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wirless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

Abstract translation: 用于经由物理总线接口进行数据汇聚和复用一个或多个虚拟总线接口的方法和装置。 各种公开的实施例被配置为：（i）通过单个物理接口复用多个逻辑接口，（ii）交换会话管理和逻辑接口控制，（iii）管理流量控制，（iv）提供关于数据的“提示” ，元数据），和/或（v）填充数据分组。 在一个特定实现中，所述方法和装置被配置为在无启用便携式电子设备（例如支持蜂窝的智能电话机）内使用，并利用高速串行物理总线接口的一个或多个特征。

公开(公告)号：US11809258B2

公开(公告)日：2023-11-07

申请号：US16820307

申请日：2020-03-16

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/4401 ,  G06F1/24

CPC classification number: G06F1/325 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F9/3004 ,  G06F9/4411 ,  G06F9/4418 ,  G06F13/404 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4278 ,  G06F1/24 ,  Y02D10/00

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

公开(公告)号：US11379278B2

公开(公告)日：2022-07-05

申请号：US17035499

申请日：2020-09-28

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F9/46 ,  G06F1/329

Abstract: Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.

公开(公告)号：US11314567B2

公开(公告)日：2022-04-26

申请号：US16691370

申请日：2019-11-21

Applicant: Apple Inc.

Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F13/362 ,  H04L25/00 ,  G06F9/46 ,  G06F13/16 ,  G06F13/42 ,  H04W84/04 ,  H04W72/12

Abstract: Methods and apparatus for scheduling time sensitive operations among independent processors. In one embodiment, an application processor (AP) determines transmission timing parameters for a baseband processor (BB). Thereafter, the AP can generate and transact generic time-sensitive real time transport (RTP) data with the BB in time for transmission via a Long Term Evolution (LTE) communication stack.

公开(公告)号：US10789110B2

公开(公告)日：2020-09-29

申请号：US16179667

申请日：2018-11-02

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F9/46 ,  G06F1/329

Abstract: Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.

公开(公告)号：US10572390B2

公开(公告)日：2020-02-25

申请号：US15273413

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F12/1009 ,  G06F8/61 ,  G06F13/42 ,  G06F1/24 ,  G06F12/14 ,  G06F3/06

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US10551902B2

公开(公告)日：2020-02-04

申请号：US15647088

申请日：2017-07-11

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/4401 ,  G06F13/42

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

公开(公告)号：US20200034186A1

公开(公告)日：2020-01-30

申请号：US16049624

申请日：2018-07-30

Applicant: Apple Inc.

Inventor： KARAN SANGHI ,  Saurabh Garg ,  Vladislav V. Petkov

IPC: G06F9/46 ,  G06F9/54

Abstract: Methods and apparatus for acknowledging and verifying the completion of data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a host-side processor delivers payloads over the IPC link using one or more transfer descriptors (TDs) that describe the payloads. The TDs are written in a particular order to a transfer descriptor ring (TR) in a shared memory between the host and peripheral processors. The peripheral reads the TDs over the IPC link and transacts, in proper order, the data retrieved based on the TDs. To acknowledge the transaction, the peripheral processor writes completion descriptors (CDs) to a completion descriptor ring (CR). The CD may complete one or more TDs; in optimized completion schemes the CD completes all outstanding TDs up to and including the expressly completed TD.

公开(公告)号：US20190317591A1

公开(公告)日：2019-10-17

申请号：US16390998

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F1/3293 ,  G06F13/42 ,  G06F1/3287 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20190227944A1

公开(公告)日：2019-07-25

申请号：US16259957

申请日：2019-01-28

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/14 ,  G06F8/61 ,  G06F1/24 ,  G06F13/42

Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.