公开(公告)号：US20140120697A1

公开(公告)日：2014-05-01

申请号：US14146887

申请日：2014-01-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模和半导体晶片的一部分进行构图，以提供图案化掩模，并在集成电路之间部分地形成沟槽而不通过半导体晶片。 每个沟槽都有一个宽度。 通过沟槽等离子体蚀刻半导体晶片以形成对应的沟槽延伸部分并对集成电路进行分割。 每个相应的沟槽延伸部具有宽度。

公开(公告)号：US11621194B2

公开(公告)日：2023-04-04

申请号：US17137099

申请日：2020-12-29

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01J37/00 ,  H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10910271B2

公开(公告)日：2021-02-02

申请号：US16885142

申请日：2020-05-27

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10714390B2

公开(公告)日：2020-07-14

申请号：US16706541

申请日：2019-12-06

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/822 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/67 ,  H01J37/32 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US09218992B2

公开(公告)日：2015-12-22

申请号：US14166715

申请日：2014-01-28

Applicant: Applied Materials, Inc.

Inventor： Saravjeet Singh ,  Brad Eaton ,  Ajay Kumar ,  Wei-Sheng Lei ,  James M. Holden ,  Madhava Rao Yalamanchili ,  Todd J. Egan

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/683 ,  H01L21/687 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40

CPC classification number: H01L21/67069 ,  B23K26/0624 ,  B23K26/064 ,  B23K26/36 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/68707 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68377

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.

Abstract translation: 对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。 一种方法包括在半导体晶片上形成掩模，掩模由覆盖并保护集成电路的层组成。 半导体晶片由衬底载体支撑。 然后用激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以在由衬底载体支撑的同时对集成电路进行分离。

公开(公告)号：US11195756B2

公开(公告)日：2021-12-07

申请号：US14491856

申请日：2014-09-19

Applicant: APPLIED MATERIALS, INC.

Inventor： James M. Holden ,  Alexander N. Lerner ,  Ajay Kumar ,  Aparna Iyer ,  Alan Hiroshi Ouye

IPC: H01J37/32 ,  H01L21/78 ,  H01L21/67 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/308

Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.

公开(公告)号：US20210134676A1

公开(公告)日：2021-05-06

申请号：US17137099

申请日：2020-12-29

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10692765B2

公开(公告)日：2020-06-23

申请号：US14536318

申请日：2014-11-07

Applicant: APPLIED MATERIALS, INC.

Inventor： James M. Holden ,  Alexander N. Lerner ,  Ajay Kumar ,  Brad Eaton ,  Aparna Iyer

IPC: H01L21/687 ,  H01L21/683 ,  H01L21/677 ,  H01L21/78 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/67 ,  H01J37/32 ,  H01L21/3213 ,  H01L21/308

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.

公开(公告)号：US10163713B2

公开(公告)日：2018-12-25

申请号：US15005700

申请日：2016-01-25

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/822 ,  H01L21/78 ,  H01L21/308 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US10112259B2

公开(公告)日：2018-10-30

申请号：US14684290

申请日：2015-04-10

Applicant: APPLIED MATERIALS, INC.

Inventor： James M. Holden ,  Nir Merry ,  Todd Egan

IPC: B23K26/06 ,  B23K26/00 ,  B23K26/36 ,  H01L21/67 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/78 ,  B23K26/364 ,  B23K26/0622 ,  B23K26/40 ,  B23K103/16 ,  B23K103/00

Abstract: Methods and apparatuses for dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating by a laser beam with a centrally peaked spatial power profile to form an ablated trench in the substrate below thin film device layers which is positively sloped. In an embodiment, a femtosecond laser forms a positively sloped ablation profile which facilitates vertically-oriented propagation of microcracks in the substrate at the ablated trench bottom. With minimal lateral runout of microcracks, a subsequent anisotropic plasma etch removes the microcracks for a cleanly singulated chip with good reliability.