公开(公告)号：US20200073749A1

公开(公告)日：2020-03-05

申请号：US16116017

申请日：2018-08-29

Applicant: Arm Limited

Inventor： Zheng XU ,  Jamshed JALAL

IPC: G06F11/07 ,  G06F13/362

Abstract: A fault tolerant data processing network includes a number of nodes intercoupled through an interconnect circuit. The micro-architectures of the nodes are configured for sending and receiving messages via the interconnect circuit. In operation, a first Request Node sends a read request to a Home Node. In response, the Home Node initiates transmission of the requested data to the first Request Node. When the first Request Node detects that a fault has occurred, it sends a negative-acknowledgement message to the first Home Node. In response, the Home Node again initiates transmission of the requested data to the first Request Node. The requested data may be transmitted from a local cache of a second Request Node or transmitted by a Slave Node after being retrieved from a memory. The data may be transmitted to the first Request Node via the Home Node or directly via the interconnect.

公开(公告)号：US20190340138A1

公开(公告)日：2019-11-07

申请号：US16027929

申请日：2018-07-05

Applicant: Arm Limited

Inventor： Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL ,  Tushar P. RINGE ,  Klas Magnus BRUCE

IPC: G06F13/16 ,  G06F12/0813 ,  G06F12/0815

Abstract: In a data processing network comprising a Request, Home and Slave Nodes coupled via a coherent interconnect, a Home Node performs a read transaction in response to a read request from a Request Node. In a first embodiment, the transaction is terminated in the Home Node upon receipt of a read receipt from a Slave Node, acknowledging a read request from the Home Node. In a second embodiment, the Home Node sends a message to the Request Node indicating that a read transaction has been ordered in the Home Node and further indicating that data for the read transaction is provided in a separate data response. The transaction is terminated in the Home Node upon receipt of an acknowledge from the Request Node of this message. In this manner, the transaction is terminated in the Home Node without waiting for acknowledgement from the Request Node of completion of the transaction.

公开(公告)号：US20180225209A1

公开(公告)日：2018-08-09

申请号：US15427320

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL ,  Mark David WERKHEISER

IPC: G06F12/0831 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897

CPC classification number: G06F12/0831 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/302 ,  G06F2212/6042

Abstract: A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.

公开(公告)号：US20170171095A1

公开(公告)日：2017-06-15

申请号：US14965237

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Ramamoorthy Guru PRASADH ,  Jamshed JALAL ,  Ashok Kumar TUMMALA ,  Phanindra Kumar MANNAVA ,  Tushar P. RINGE

IPC: H04L12/891 ,  H04L12/835 ,  H04L29/06 ,  H04L12/26

CPC classification number: H04L47/41 ,  H04L43/106 ,  H04L43/16 ,  H04L47/30 ,  H04L69/08 ,  H04L69/18 ,  H04L69/22

Abstract: A bridging circuit and method of operation thereof, which couples first and second electronic circuits of a data processing system. The first electronic circuit generates signals corresponding to digits of a flow control unit (flit) of a first flow control protocol and where the second electronic circuit is responsive to signals corresponding to flits of a second flow control protocol. When first flits are destined for the same target buffer, they are combined to provide a second flit consistent with the second flow control protocol and transmitting the second flit to the second electronic circuit. The second flit includes data and metadata fields copied from the first flits, a common field common to each of the first flits, a merged field containing a merger of fields from the first flits and a validity field indicating which portions of the second flit contain valid data.

公开(公告)号：US20160062890A1

公开(公告)日：2016-03-03

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Jamshed JALAL ,  Mark David WERKHEISER ,  Arthur LAUGHTON ,  George Robert Scott LLOYD ,  Peter Andrew RIOCREUX ,  Daniel SARA

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。

公开(公告)号：US20230418766A1

公开(公告)日：2023-12-28

申请号：US18253621

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Klas Magnus BRUCE ,  Jamshed JALAL ,  Dimitrios KASERIDIS ,  Gurunath RAMAGIRI ,  Ho-Seop KIM ,  Andrew John TURNER ,  Rania Hussein Hassan MAMEESH

IPC: G06F12/126 ,  G06F12/0811

CPC classification number: G06F12/126 ,  G06F12/0811

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.

公开(公告)号：US20210216241A1

公开(公告)日：2021-07-15

申请号：US16743409

申请日：2020-01-15

Applicant: Arm Limited

Inventor： Gurunath RAMAGIRI ,  Jamshed JALAL ,  Mark David WERKHEISER ,  Tushar P. RINGE ,  Klas Magnus BRUCE ,  Ritukar KHANNA

IPC: G06F3/06

Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

公开(公告)号：US20210103524A1

公开(公告)日：2021-04-08

申请号：US16595863

申请日：2019-10-08

Applicant: Arm Limited

Inventor： Bruce James MATHEWSON ,  Phanindra Kumar MANNAVA ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Andrew John TURNER

IPC: G06F12/0815 ,  G06F9/52

Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.

公开(公告)号：US20200167284A1

公开(公告)日：2020-05-28

申请号：US16202171

申请日：2018-11-28

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Mark David WERKHEISER ,  Michael FILIPPO ,  Klas Magnus BRUCE ,  Paul Gilbert MEYER

IPC: G06F12/0815 ,  G06F13/16

Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.

公开(公告)号：US20200050568A1

公开(公告)日：2020-02-13

申请号：US16659762

申请日：2019-10-22

Applicant: Arm Limited

Inventor： Guanghui GENG ,  Andrew David TUNE ,  Daniel Adam SARA ,  Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL

IPC: G06F13/364 ,  G06F12/0815 ,  G06F12/0888 ,  G06F13/40 ,  G06F13/42

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.