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    Memory device and method of operation of such a memory device
    12.
    发明授权
    Memory device and method of operation of such a memory device 有权
    这种存储器件的存储器件和操作方法

    公开(公告)号：US08971133B1

    公开(公告)日：2015-03-03

    申请号：US14037413

    申请日：2013-09-26

    Applicant: ARM Limited

    Inventor： Bo Zheng ,  Jungtae Kwon ,  Gus Yeung ,  Yew Keong Chong

    IPC: G11C7/10 ,  G11C7/22 ,  G11C7/12 ,  G06F17/50

    CPC classification number: G11C7/12 ,  G11C7/1096

    Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

    Abstract translation: 具有连接到核心电压电平的存储器单元阵列的存储器件，以及用于执行写入操作以便将数据写入到多个寻址的存储器单元中的存取电路。 在执行写入操作之前，至少与包含寻址的存储器单元的阵列中的每列相关联的位线被预充电到外围电压电平。 然后，字线驱动器电路被配置为在与包含寻址的存储器单元的阵列的行相关联的字线上的核心电压电平处断言字线信号。 写复用驱动器电路断言多路复用控制信号以写入多路复用电路，然后根据多路复用器控制信号将每个寻址的存储器单元的位线耦合到写入驱动器电路，该多路复用器控制信号标识哪个列包含寻址的存储器单元。

    Circuits and methods for capacitor modulation
    14.
    发明授权
    Circuits and methods for capacitor modulation 有权

    公开(公告)号：US11574660B2

    公开(公告)日：2023-02-07

    申请号：US16989883

    申请日：2020-08-11

    Applicant: Arm Limited

    Inventor： Lalit Gupta ,  Nimish Sharma ,  Hetansh Pareshbhai Shah ,  Bo Zheng

    IPC: G11C7/10 ,  G11C7/06 ,  G11C16/26 ,  G11C16/10

    Abstract: In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.

    Memory Access Techniques
    16.
    发明申请
    Memory Access Techniques 有权

    公开(公告)号：US20210110853A1

    公开(公告)日：2021-04-15

    申请号：US16600483

    申请日：2019-10-12

    Applicant: Arm Limited

    Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes van Windelhoff ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

    IPC: G11C7/10 ,  G11C11/419 ,  G11C11/418 ,  G11C11/16

    Abstract: Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.

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