公开(公告)号：US20160133628A1

公开(公告)日：2016-05-12

申请号：US14997683

申请日：2016-01-18

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/165

Abstract: Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both n-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.

Abstract translation: 公开了形成结构和装置的半导体结构，器件和方法。 示例性结构包括可以包括n沟道MOS（NMOS）和p沟道MOS（PMOS）器件的多栅极或FinFET结构，以在衬底上形成CMOS结构和器件。 可以使用选择性外延和浅沟槽隔离技术来形成器件。

公开(公告)号：US20140322862A1

公开(公告)日：2014-10-30

申请号：US14256728

申请日：2014-04-18

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes ,  Michael Givens ,  Petri Raisanen

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  G11C13/0007 ,  G11C2213/71 ,  H01L45/08 ,  H01L45/085 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1641

Abstract: A method for forming a resistive random access memory (RRAM) device is disclosed. The method comprises forming a first electrode, forming a resistive switching oxide layer comprising a metal oxide by thermal atomic layer deposition (ALD), doping the resistive switching oxide layer with a metal dopant different from metal forming the metal oxide, and forming a second electrode by thermal atomic layer deposition (ALD), where the resistive switching layer is interposed between the first electrode and the second electrode. In some embodiments, forming the resistive switching oxide may be performed without exposing a surface of the switching oxide layer to a surface-modifying plasma treatment after depositing the metal oxide.

Abstract translation: 公开了一种形成电阻随机存取存储器（RRAM）装置的方法。 该方法包括：形成第一电极，通过热原子层沉积（ALD）形成包含金属氧化物的电阻式开关氧化物层，用与形成金属氧化物的金属不同的金属掺杂剂掺杂电阻式开关氧化物层，以及形成第二电极 通过热原子层沉积（ALD），其中电阻式开关层介于第一电极和第二电极之间。 在一些实施例中，在沉积金属氧化物之后，可以进行形成电阻式开关氧化物而不使开关氧化物层的表面暴露于表面改性等离子体处理。

公开(公告)号：US08841182B1

公开(公告)日：2014-09-23

申请号：US13829856

申请日：2013-03-14

Applicant: ASM IP Holding B.V.

Inventor： Jerry Chen ,  Vladimir Machkaoutsan ,  Brennan Milligan ,  Jan Willem Maes ,  Suvi Haukka ,  Eric Shero ,  Tom E. Blomberg ,  Dong Li

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/28088 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/28044 ,  H01L21/2807 ,  H01L21/28556 ,  H01L21/28568

Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film including titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that includes titanium and at least one halide ligand, a second source chemical that includes metal and carbon, where the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, where the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. The treatment can form a capping layer on the metal carbide film.

Abstract translation: 提供了用含有碳化钛的薄膜与含硅烷/硼烷剂一起处理含金属薄膜的方法。 在一些实施例中，包括碳化钛的膜通过原子层沉积（ALD）工艺沉积在衬底上。 该方法可以包括多个沉积循环，其涉及包括钛和至少一种卤化物配体的第一源化学品的交替和顺序脉冲，第二源化学物质包括金属和碳，其中来自第二源化学物质的金属和碳 和第三源化学品，其中第三源化学品是至少部分地减少由第一和第二源化学品形成的碳化钛层的氧化部分的硅烷或硼烷。 处理可以在金属碳化物膜上形成覆盖层。

公开(公告)号：US09583348B2

公开(公告)日：2017-02-28

申请号：US14987413

申请日：2016-01-04

Applicant: ASM IP Holding B.V.

Inventor： Jerry Chen ,  Vladimir Machkaoutsan ,  Brennan Milligan ,  Jan Maes ,  Suvi Haukka ,  Eric Shero ,  Tom Blomberg ,  Dong Li

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L21/28088 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/28044 ,  H01L21/2807 ,  H01L21/28556 ,  H01L21/28568

Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film comprising titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that comprises titanium and at least one halide ligand, a second source chemical comprising metal and carbon, wherein the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, wherein the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. In some embodiments treatment forms a capping layer on the metal carbide film.

Abstract translation: 提供了用含有碳化钛的薄膜与含硅烷/硼烷剂一起处理含金属薄膜的方法。 在一些实施方案中，包含碳化钛的膜通过原子层沉积（ALD）工艺沉积在衬底上。 该方法可以包括多个沉积循环，其涉及包含钛和至少一种卤化物配体的第一源化学品的交替和顺序脉冲，包含金属和碳的第二源化学物质，其中来自第二源化学物质的金属和碳 和第三源化学品，其中第三源化学品是至少部分地减少由第一和第二源化学品形成的碳化钛层的氧化部分的硅烷或硼烷。 在一些实施方案中，处理在金属碳化物膜上形成覆盖层。

公开(公告)号：US20150214301A1

公开(公告)日：2015-07-30

申请号：US14678301

申请日：2015-04-03

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0254 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/057 ,  Y10S977/89 ,  Y10S977/938

Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

Abstract translation: 在一些实施例中，制造方法形成诸如晶体管的半导体器件。 在半导体衬底上形成电介质叠层。 堆叠包括由多个间隔层之一隔开的多个电介质层。 多个间隔层中的每一个由与多个电介质层的紧邻层不同的材料形成。 通过多个介电层和多个间隔层形成垂直延伸的孔。 通过进行外延沉积来填充孔，其中材料填充形成线的孔。 导线被掺杂，并且三个电介质层被顺序地移除并被导电材料代替，由此形成上部和下部接触线和上部和下部触点之间的栅极。 导线可以用作晶体管的沟道区。

公开(公告)号：US20150091057A1

公开(公告)日：2015-04-02

申请号：US14040196

申请日：2013-09-27

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/165

Abstract: Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.

Abstract translation: 公开了形成结构和装置的半导体结构，器件和方法。 示例性结构包括可以包括再通道MOS（NMOS）和p沟道MOS（PMOS）器件的多栅极或FinFET结构，以在衬底上形成CMOS结构和器件。 可以使用选择性外延和浅沟槽隔离技术来形成器件。

公开(公告)号：US20140322885A1

公开(公告)日：2014-10-30

申请号：US13872932

申请日：2013-04-29

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes ,  Michael Givens ,  Petri Raisanen

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146

Abstract: A method for forming a resistive random access memory (RRAM) device is disclosed. The method comprises forming a first electrode, forming a resistive switching oxide layer comprising a metal oxide by thermal atomic layer deposition (ALD) and forming a second electrode by thermal atomic layer deposition (ALD), where the resistive switching layer is interposed between the first electrode and the second electrode. Forming the resistive switching oxide may be performed without exposing a surface of the switching oxide layer to a surface-modifying plasma treatment after depositing the metal oxide.

Abstract translation: 公开了一种形成电阻随机存取存储器（RRAM）装置的方法。 该方法包括形成第一电极，通过热原子层沉积（ALD）形成包括金属氧化物的电阻式切换氧化物层，并通过热原子层沉积（ALD）形成第二电极，其中电阻式开关层介于第一 电极和第二电极。 可以在沉积金属氧化物之后，进行电阻式开关氧化物的形成而不使开关氧化物层的表面暴露于表面改性等离子体处理。

公开(公告)号：US20140030859A1

公开(公告)日：2014-01-30

申请号：US14045680

申请日：2013-10-03

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

IPC: H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0254 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/057 ,  Y10S977/89 ,  Y10S977/938

Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

Abstract translation: 在一些实施例中，制造方法形成诸如晶体管的半导体器件。 在半导体衬底上形成电介质叠层。 堆叠包括由多个间隔层之一隔开的多个电介质层。 多个间隔层中的每一个由与多个电介质层的紧邻层不同的材料形成。 通过多个介电层和多个间隔层形成垂直延伸的孔。 通过进行外延沉积来填充孔，其中材料填充形成线的孔。 导线被掺杂，并且三个电介质层被顺序地移除并被导电材料代替，由此形成上部和下部接触线和上部和下部触点之间的栅极。 导线可以用作晶体管的沟道区。