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    ACCESS LOG AND ADDRESS TRANSLATION LOG FOR A PROCESSOR
    11.
    发明申请
    ACCESS LOG AND ADDRESS TRANSLATION LOG FOR A PROCESSOR 审中-公开
    访问日志和地址处理器的翻译日志

    公开(公告)号：US20160378682A1

    公开(公告)日：2016-12-29

    申请号：US14747980

    申请日：2015-06-23

    Applicant: Avanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Mike Mantor

    IPC: G06F12/10 ,  G06F12/12 ,  G06F12/08

    CPC classification number: G06F12/1027 ,  G06F12/0893 ,  G06F2212/684

    Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

    Abstract translation: 处理器在处理器的高速缓存中维护指示高速缓存未命中流的访问日志。 响应于高速缓存的高速缓存未命中的至少一个子集中的每一个，处理器在访问日志中记录相应的条目，指示导致相应的未命中的存储器访问请求的物理存储器地址。 此外，处理器维护地址转换日志，其指示物理存储器地址与虚拟存储器地址的映射。 响应于将虚拟地址转换为物理地址的地址转换（例如，寻路步行），处理器在地址转换日志的条目处存储物理地址与对应的虚拟地址的映射。 处理器执行的软件可以使用两个日志进行内存管理。

    MANAGING COHERENT MEMORY BETWEEN AN ACCELERATED PROCESSING DEVICE AND A CENTRAL PROCESSING UNIT
    12.
    发明申请
    MANAGING COHERENT MEMORY BETWEEN AN ACCELERATED PROCESSING DEVICE AND A CENTRAL PROCESSING UNIT 审中-公开
    管理加速处理装置与中央处理装置之间的相关记忆

    公开(公告)号：US20160364334A1

    公开(公告)日：2016-12-15

    申请号：US15246056

    申请日：2016-08-24

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

    IPC: G06F12/0815 ,  G06F12/0804

    CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0835 ,  G06F12/0837 ,  G06F12/0848 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

    Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

    Abstract translation: 现有的多处理器计算系统通常具有不足的存储器一致性，因此不能有效地利用单独的存储器系统。 具体来说，CPU无法有效地写入内存块，然后除了有明确的同步之外，还可以对存储器进行GPU访问。 另外，由于GPU被迫静态分割其本身与CPU之间的存储器位置，所以现有的多处理器计算系统不能有效地利用单独的存储器系统。 本文所描述的实施例通过在GPU内接收到通知，CPU已经完成处理存储在相干存储器中的数据，并使CPU缓冲器中的数据无效，GPU已经从相干存储器完成处理来克服这些缺陷。 本文描述的实施例还包括通过使用探针滤波器来将GPU存储器动态地划分为相干存储器和本地存储器。

    INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE
    14.
    发明申请
    INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE 有权
    输入/输出存储器映射单元和北桥

    公开(公告)号：US20150120978A1

    公开(公告)日：2015-04-30

    申请号：US14523705

    申请日：2014-10-24

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Maggie Chan ,  Vincent Cueva ,  Liang Chen ,  Anthony Asaro ,  Jimshed Mirza ,  Greggory D. Donley ,  Bryan Broussard ,  Benjamin Tsien ,  Yaniv Adiri

    IPC: G06F12/10 ,  G06F13/24 ,  G06F12/12

    CPC classification number: G06F12/1009 ,  G06F12/1045 ,  G06F12/12 ,  G06F2212/684

    Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

    Abstract translation: 本发明通过新的原子测试[0]和OR和Mask来提供在硬件中的页表访问和脏位管理。 本发明还提供了一种使ACE能够进行CCI翻译的垫圈。 该垫片进一步提供了ACE和CCI之间的请求转换，针对受害者和探针冲突的死锁避免，ARM屏障处理和电源管理交互。 本发明还提供了一种用于ARM受害者/探测器碰撞处理的解决方案，其使统一的北桥陷入僵局。 这些解决方案包括一个专用的回写虚拟通道，使用4跳协议的IO请求的探测器和MCT中的WrBack重新排序能力，其中受害者通过数据通过请求时更新旧的请求。

    METHOD AND APPARATUS FOR MANAGING MEMORY
    17.
    发明公开
    METHOD AND APPARATUS FOR MANAGING MEMORY 审中-公开

    公开(公告)号：US20240201876A1

    公开(公告)日：2024-06-20

    申请号：US18083306

    申请日：2022-12-16

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Lu Lu ,  Anthony Asaro ,  Yinan Jiang

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673

    Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

    Hang detection for virtualized accelerated processing device
    20.
    发明授权
    Hang detection for virtualized accelerated processing device 有权

    公开(公告)号：US11182186B2

    公开(公告)日：2021-11-23

    申请号：US15663499

    申请日：2017-07-28

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Anthony Asaro ,  Yinan Jiang ,  Andy Sung ,  Ahmed M. Abdelkhalek ,  Xiaowei Wang ,  Sidney D. Fortes

    IPC: G06F9/46 ,  G06F9/455 ,  G06F9/48

    Abstract: A technique for recovering from a hang in a virtualized accelerated processing device (“APD”) is provided. In the virtualization scheme, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD stops operations for a current VM and starts operations for another VM. To stop operations on the APD, a virtualization scheduler sends a request to idle the APD. The APD responds by completing work and idling. If one or more portions of the APD do not complete this idling process before a timeout expires, then a hang occurs. In response to the hang, the virtualization scheduler informs the hypervisor that a hang has occurred. The hypervisor performs a function level reset on the APD and informs the VM that the hang has occurred. The VM responds by stopping command issue to the APD and re-initializing the APD for the function.

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