公开(公告)号：US07948030B2

公开(公告)日：2011-05-24

申请号：US12875828

申请日：2010-09-03

Applicant: Larson Lindholm ,  Aaron R. Wilson ,  David K. Hwang

Inventor： Larson Lindholm ,  Aaron R. Wilson ,  David K. Hwang

IPC: H01L29/76

CPC classification number: H01L27/10891 ,  H01L21/31116 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.

Abstract translation: 一些实施方案包括使用包含C 4 F 6和C 4 F 3的蚀刻剂将多种材料凹入共同深度的方法。 凹陷的材料可以在隔离区域内，并且凹陷可以用于形成用于接收基准线的沟槽。 一些实施例包括具有由电绝缘材料横向包围的半导体材料岛的结构。 两种栅极延伸穿过绝缘材料和半导体材料岛。 电绝缘材料中的一种比另一种更凹陷。

公开(公告)号：US20110057269A1

公开(公告)日：2011-03-10

申请号：US12944529

申请日：2010-11-11

Applicant: Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

IPC: H01L27/088

CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。 在一些实施例中，通过使用一对浅沟槽隔离（STI）结构作为掩模来减薄浅沟槽隔离结构来形成双鳍结构，以在该一对STI结构之间限定衬底的一部分中的凹陷，以及凹陷 STI结构使得所得到的双翅片结构从基板的有效表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

公开(公告)号：US07857982B2

公开(公告)日：2010-12-28

申请号：US11185229

申请日：2005-07-19

Applicant: Mirzafer Abatchev ,  Gurtej S. Sandhu ,  Aaron R. Wilson ,  Tony Schrock

Inventor： Mirzafer Abatchev ,  Gurtej S. Sandhu ,  Aaron R. Wilson ,  Tony Schrock

IPC: H01L21/302

CPC classification number: H01L21/3081 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/906 ,  Y10S438/945

Abstract: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.

Abstract translation: 本发明包括将特征蚀刻到基底中的方法。 在待蚀刻的基板的材料上形成多个硬掩模层。 在这样的层中形成特征图案。 使用其中具有特征图案的硬掩模层作为掩模，将特征部分地蚀刻到基底材料中。 在部分蚀刻之后，相对于衬底材料选择性蚀刻至少一个硬掩模层，并保留硬掩模层。 在蚀刻至少一个硬掩模层之后，使用至少最内侧的硬掩模层作为掩模将特征进一步蚀刻到基底材料中。 在进一步蚀刻之后，从衬底去除最内层的硬掩模层和剩余的硬掩模层，并且将特征的至少一部分结合到集成电路中。

公开(公告)号：US07808041B2

公开(公告)日：2010-10-05

申请号：US12628910

申请日：2009-12-01

Applicant: Larson Lindholm ,  Aaron R. Wilson ,  David K. Hwang

Inventor： Larson Lindholm ,  Aaron R. Wilson ,  David K. Hwang

IPC: H01L29/76

CPC classification number: H01L27/10891 ,  H01L21/31116 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.

Abstract translation: 一些实施方案包括使用包含C 4 F 6和C 4 F 8的蚀刻剂将多种材料凹陷到共同深度的方法。 凹陷的材料可以在隔离区域内，并且凹陷可以用于形成用于接收基准线的沟槽。 一些实施例包括具有由电绝缘材料横向包围的半导体材料岛的结构。 两种栅极延伸穿过绝缘材料和半导体材料岛。 电绝缘材料中的一种比另一种更凹陷。

公开(公告)号：US07670958B2

公开(公告)日：2010-03-02

申请号：US11497702

申请日：2006-08-01

Applicant: Aaron R. Wilson

Inventor： Aaron R. Wilson

IPC: H01L21/302

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: An etching method includes applying a photoresist over a substrate, forming an opening in the photoresist, and etching the substrate under the opening using a plasma generated with a gas composition containing argon and an amount of higher atomic mass inert gas. The amount may be effective to increase photoresist stability compared to otherwise identical etching lacking any of the higher atomic mass inert gas. The photoresist may have a composition sensitized to an actinic energy wavelength of 248 nm or less. A method of increasing the stability of 248 nm or less photoresist during RIE includes providing a means for reducing electron temperature of a plasma and etching a substrate exposed through photoresist openings without substantially destabilizing the photoresist.

Abstract translation: 蚀刻方法包括在基板上施加光致抗蚀剂，在光致抗蚀剂中形成开口，以及使用包含氩气和一定量的较高原子质量惰性气体的气体组合物产生的等离子体在开口下蚀刻基板。 与不存在任何较高原子质量惰性气体的相同蚀刻相比，该量可以有效地增加光致抗蚀剂的稳定性。 光致抗蚀剂可以具有对248nm或更小的光化能量波长敏化的组成。 在RIE期间增加248nm或更小的光致抗蚀剂的稳定性的方法包括提供降低等离子体的电子温度并蚀刻通过光致抗蚀剂开口暴露的基板的方法，而基本上不使光致抗蚀剂稳定。

公开(公告)号：US06461526B1

公开(公告)日：2002-10-08

申请号：US09639357

申请日：2000-08-14

Applicant: Aaron R. Wilson

Inventor： Aaron R. Wilson

IPC: H01J904

CPC classification number: H01J9/025

Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.

公开(公告)号：US06358763B1

公开(公告)日：2002-03-19

申请号：US09545978

申请日：2000-04-10

Applicant: David H. Wells ,  Aaron R. Wilson ,  John J. Michiels

Inventor： David H. Wells ,  Aaron R. Wilson ,  John J. Michiels

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01L21/027

Abstract: Methods of forming mask patterns and methods of forming field emitter tip masks are described. In one embodiment a first surface is provided over which a mask pattern is to be formed. A mixture comprising mask particles is applied to a second surface comprising material joined with the first layer. The mixture, as applied, leaves an undesirable distribution of mask particles over the first surface. After application of the mixture to the second surface, the mask particles are laterally distributed over the first surface, into a desirable distribution by placing a particle-dispersing structure directly into the mixture on the second surface and moving the particle-dispersing structure laterally through the mixture on the second surface. In another embodiment, a mixture is formed on the substrate's second surface and includes a liquid component and a plurality of solid mask-forming components. A mixture-thinning structure is positioned over the substrate and separated from the second surface thereof only by the mixture. The mixture-thinning structure is moved through the mixture in a manner which forms at least some of the mask-forming components into a monolayer of single mask components over the second surface.

Abstract translation: 描述形成掩模图案的方法和形成场发射器尖端掩模的方法。 在一个实施例中，提供了要形成掩模图案的第一表面。 将包含掩模颗粒的混合物施加到包含与第一层连接的材料的第二表面。 如所施加的，混合物在第一表面上留下不希望的掩模颗粒分布。 在将混合物施加到第二表面之后，掩模颗粒横向分布在第一表面上，通过将颗粒分散结构直接放置在第二表面上的混合物中并将颗粒分散结构横向移动通过 混合物在第二表面上。 在另一个实施例中，在基板的第二表面上形成混合物，并且包括液体组分和多个固体掩模形成组分。 混合物稀化结构位于衬底上并且仅通过混合物与第二表面分离。 混合物稀化结构以在至少一些掩模形成组分形成单层掩模组分的第二表面的单层的方式移动通过混合物。

公开(公告)号：US6143580A

公开(公告)日：2000-11-07

申请号：US251176

申请日：1999-02-17

Applicant: David H. Wells ,  Aaron R. Wilson ,  John J. Michiels

Inventor： David H. Wells ,  Aaron R. Wilson ,  John J. Michiels

IPC: H01J9/02 ,  H01L21/027

CPC classification number: H01J9/025 ,  H01L21/027

Abstract: Methods of forming mask patterns and methods of forming field emitter tip masks are described. In one embodiment a first surface is provided over which a mask pattern is to be formed. A mixture comprising mask particles is applied to a second surface comprising material joined with the first layer. The mixture, as applied, leaves an undesirable distribution of mask particles over the first surface. After application of the mixture to the second surface, the mask particles are laterally distributed over the first surface, into a desirable distribution by placing a particle-dispersing structure directly into the mixture on the second surface and moving the particle-dispersing structure laterally through the mixture on the second surface. In another embodiment, a mixture is formed on the substrate's second surface and includes a liquid component and a plurality of solid mask-forming components. A mixture-thinning structure is positioned over the substrate and separated from the second surface thereof only by the mixture. The mixture-thinning structure is moved through the mixture in a manner which forms at least some of the mask-forming components into a monolayer of single mask components over the second surface.

公开(公告)号：US08138526B2

公开(公告)日：2012-03-20

申请号：US12944529

申请日：2010-11-11

Applicant: Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: Fin-FET（鳍场效应晶体管）器件及其制造方法。 Fin-FET器件包括双鳍结构，其可以在源极区域和漏极区域之间形成沟道区域。 在一些实施例中，通过使用一对浅沟槽隔离（STI）结构作为掩模来减薄浅沟槽隔离结构来形成双鳍结构，以在该一对STI结构之间限定衬底的一部分中的凹陷，以及凹陷 所述一对STI结构使得所得到的双翅片结构从所述基板的有源表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

公开(公告)号：US08093725B2

公开(公告)日：2012-01-10

申请号：US12569561

申请日：2009-09-29

Applicant: Aaron R. Wilson

Inventor： Aaron R. Wilson

IPC: H01L29/40

CPC classification number: H01L21/31116 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/31138

Abstract: A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating layer to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1. Secondly, the insulating layer is exposed to a first plasma of a first gaseous etchant having at least fifty percent helium (He) to etch the opening having an aspect ratio of at least 15:1, thereby increasing the aspect ratio to greater than 15:1, where the first gaseous etchant has a lower molecular weight than the second gaseous etchant.

Abstract translation: 根据用于蚀刻绝缘层的方法形成的触点，以通过首先将绝缘层暴露于包含Ar，Xe的第二气态蚀刻剂的第二等离子体及其组合来形成具有至少15:1的纵横比的开口 以形成长宽比小于15:1的开口。 其次，绝缘层暴露于具有至少50％的氦（He）的第一气态蚀刻剂的第一等离子体，以蚀刻具有至少15:1的纵横比的开口，从而将纵横比增加到大于15:1。 1，其中第一气体蚀刻剂具有比第二气体蚀刻剂更低的分子量。