公开(公告)号：US11140107B2

公开(公告)日：2021-10-05

申请号：US15418369

申请日：2017-01-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew G. Kegel ,  Arkaprava Basu

IPC: G06F15/16 ,  H04L12/58 ,  G06Q10/10 ,  G06F15/173

Abstract: Various messaging systems and methods are disclosed for meeting invitation management. In one aspect, a method of messaging is provided that includes generating a message to invite one or more invitees to a meeting. The message includes an assertion to suppress an auto-responder of the one or more invitees. The message is sent to the one or more invitees. The assertion suppresses the auto-responder of the one or more invitees.

公开(公告)号：US20190384722A1

公开(公告)日：2019-12-19

申请号：US16007027

申请日：2018-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Michael LeBeane ,  Eric Van Tassell

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/50 ,  G06F9/48 ,  G06F13/16 ,  G06F13/22

Abstract: A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

公开(公告)号：US10437736B2

公开(公告)日：2019-10-08

申请号：US15852442

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Eric Van Tassell ,  Mark Oskin ,  Guilherme Cox ,  Gabriel Loh

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F13/40 ,  G06F9/48 ,  G06F13/42

Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

公开(公告)号：US20190286362A1

公开(公告)日：2019-09-19

申请号：US16432391

申请日：2019-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mitesh R. Meswani ,  Dibakar Gope ,  Sooraj Puthoor

IPC: G06F3/06 ,  G06F12/02

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

公开(公告)号：US20190196978A1

公开(公告)日：2019-06-27

申请号：US15852442

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Eric Van Tassell ,  Mark Oskin ,  Guilherme Cox ,  Gabriel Loh

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F13/40 ,  G06F13/42 ,  G06F9/48

CPC classification number: G06F12/1009 ,  G06F9/3887 ,  G06F9/4843 ,  G06F12/1027 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2213/0026

Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

公开(公告)号：US09983655B2

公开(公告)日：2018-05-29

申请号：US14963352

申请日：2015-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Dmitri Yudanov ,  Arkaprava Basu ,  Sergey Blagodurov

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3243 ,  G06F9/3885

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

公开(公告)号：US20170277639A1

公开(公告)日：2017-09-28

申请号：US15361335

申请日：2016-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov ,  Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/65 ,  G06F2212/683

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.

公开(公告)号：US10592279B2

公开(公告)日：2020-03-17

申请号：US15191355

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Dmitri Yudanov ,  David A. Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov

IPC: G06F9/52 ,  G06F9/48 ,  G06F11/34 ,  G06F9/50

Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.

公开(公告)号：US20190317807A1

公开(公告)日：2019-10-17

申请号：US15954382

申请日：2018-04-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Joseph Lee Greathouse

IPC: G06F9/48 ,  G06F9/46

Abstract: Systems, apparatuses, and methods for enforcing processor quality of service guarantees when servicing system service requests (SSRs) are disclosed. A system includes a first processor executing an operating system and a second processor executing an application which generates SSRs for the first processor to service. The first processor monitors the number of cycles spent servicing SSRs over a previous time interval, and if this number of cycles is above a threshold, the first processor starts delaying the servicing of subsequent SSRs. In one implementation, if the previous delay was non-zero, the first processor increases the delay used in the servicing of subsequent SSRs. If the number of cycles is less than or equal to the threshold, then the first processor services SSRs without delay. As the delay is increased, the second processor begins to stall and its SSR generation rate falls, reducing the load on the first processor.

公开(公告)号：US20180314436A1

公开(公告)日：2018-11-01

申请号：US15499313

申请日：2017-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Jee Ho Ryoo

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/1009

Abstract: The present disclosure is directed to techniques for migrating data between heterogeneous memories in a computing system. More specifically, the techniques involve migrating data between a memory having better access characteristics (e.g., lower latency but greater capacity) and a memory having worse access characteristics (e.g., higher latency but lower capacity). Migrations occur with a variable migration granularity. A migration granularity specifies a number of memory pages, having virtual addresses that are contiguous in virtual address space, that are migrated in a single migration operation. A history-based technique that adjusts migration granularity based on the history of memory utilization by an application is provided. A profiling-based technique that adjusts migration granularity based on a profiling operation is also provided.