公开(公告)号：US20200293445A1

公开(公告)日：2020-09-17

申请号：US16355168

申请日：2019-03-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mohamed Assem IBRAHIM ,  Onur KAYIRAN ,  Yasuko ECKERT ,  Gabriel H. LOH

IPC: G06F12/0802

Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.

公开(公告)号：US20140136873A1

公开(公告)日：2014-05-15

申请号：US13676805

申请日：2012-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mauricio BRETERNITZ ,  James M. O'CONNOR ,  Gabriel H. LOH ,  Yasuko ECKERT ,  Mithuna THOTTETHODI ,  Srilatha MANNE ,  Bradford M. BECKMANN

IPC: G06F1/28

CPC classification number: G06F1/3275 ,  Y02D10/14 ,  Y02D50/20

Abstract: A device receives an indication that a memory bank is to be powered up, and determines, based on receiving the indication, power scores corresponding to powered down memory banks. Each power score corresponds to a power metric associated with powering up a powered down memory bank. The device powers up a selected memory bank based on the plurality of power scores.

Abstract translation: 设备接收到存储器组将被加电的指示，并且基于接收到该指示确定对应于掉电存储器组的功率分数。 每个功率分数对应于与断电存储器组的加电相关联的功率度量。 设备基于多个功率得分来加电所选择的存储体。

公开(公告)号：US20200278930A1

公开(公告)日：2020-09-03

申请号：US16821632

申请日：2020-03-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yasuko ECKERT ,  Maurice B. STEINMAN ,  Steven RAASCH

IPC: G06F12/0817 ,  G06F12/084

Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.

公开(公告)号：US20190163632A1

公开(公告)日：2019-05-30

申请号：US15825880

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. WALKER ,  Michael W. BOYER ,  Yasuko ECKERT ,  Gabriel H. LOH

IPC: G06F12/0817 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811

Abstract: A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.

公开(公告)号：US20180285264A1

公开(公告)日：2018-10-04

申请号：US15475435

申请日：2017-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur KAYIRAN ,  Gabriel H. LOH ,  Yasuko ECKERT

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/621

Abstract: A processing system includes at least one central processing unit (CPU) core, at least one graphics processing unit (GPU) core, a main memory, and a coherence directory for maintaining cache coherence. The at least one CPU core receives a CPU cache flush command to flush cache lines stored in cache memory of the at least one CPU core prior to launching a GPU kernel. The coherence directory transfers data associated with a memory access request by the at least one GPU core from the main memory without issuing coherence probes to caches of the at least one CPU core.

公开(公告)号：US20160170887A1

公开(公告)日：2016-06-16

申请号：US14569175

申请日：2014-12-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Syed Ali R. JAFRI ,  Yasuko ECKERT ,  Srilatha MANNE ,  Mithuna S. THOTTETHODI ,  Gabriel H. LOH

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/62 ,  Y02D10/13

Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.

Abstract translation: 为了有效地将数据从高速缓存传输到存储器，期望将与存储器中的相同页面相对应的更多数据加载到行缓冲器中。 将数据写入当前未加载到行缓冲区的内存页面时，需要关闭旧页面并打开新页面。 两种操作都消耗能量和时钟周期，并可能延迟更多关键的存储器读取请求。 因此，期望具有多于一个写入同一DRAM页面的写入以分摊打开和关闭DRAM页面的成本。 期望的方法是通过将修改的块保留在高速缓存中来批量回写到相同的DRAM页面，直到属于同一存储器页面的足够数量的修改的块准备好回写。

公开(公告)号：US20150121106A1

公开(公告)日：2015-04-30

申请号：US14068207

申请日：2013-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko ECKERT ,  Manish Arora

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3231 ,  G06F1/324 ,  G06F1/3246 ,  Y02D10/126 ,  Y02D10/173

Abstract: An approach is described herein that includes a method for power management of a device. In one example, the method includes sampling duration characteristics for a plurality of past idle events for a predetermined interval of time and determining whether to transition a device to a powered-down state based on the sampled duration characteristics. In another example, the method includes determining whether an average idle time for a plurality of past idle events exceeds an energy break-even point threshold. If the average idle time for the plurality of past idle events exceeds the energy break-even point threshold, a device is immediately transitioned to a powered-down state upon receipt of a next idle event. If the average idle time for the plurality of past idle events does not exceed the energy break-even point threshold, transition of the device to the powered-down state is delayed.

Abstract translation: 这里描述了包括用于设备的电源管理的方法的方法。 在一个示例中，该方法包括在预定的时间间隔内对多个过去的空闲事件采样持续时间特征，并且基于采样的持续时间特性来确定是否将设备转换到掉电状态。 在另一示例中，该方法包括确定多个过去的空闲事件的平均空闲时间是否超过能量中断点阈值。 如果多个过去的空闲事件的平均空闲时间超过能量中断点阈值，则在接收到下一个空闲事件时，设备立即转换到掉电状态。 如果多个过去的空闲事件的平均空闲时间不超过能量中断点阈值，则设备转换到掉电状态被延迟。