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    Frequency/state based power management thresholds
    13.
    发明授权
    Frequency/state based power management thresholds 有权

    公开(公告)号：US12164353B2

    公开(公告)日：2024-12-10

    申请号：US17936740

    申请日：2022-09-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Shang Yang

    IPC: G06F1/3206

    Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI
    14.
    发明公开
    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI 审中-公开

    公开(公告)号：US20240334340A1

    公开(公告)日：2024-10-03

    申请号：US18128805

    申请日：2023-03-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Paul Blinzer ,  Chirag Nitinkumar Dhruv ,  Ranjeet Kumar ,  Gia Tung Phan ,  Ashish Jain

    IPC: H04W52/02

    CPC classification number: H04W52/029 ,  H04W52/0274

    Abstract: An apparatus and method for efficiently performing power management for increasing reliable wireless signal transfer performed by mobile computing devices. In various implementations, a computing system includes a network interface and multiple components for processing tasks. The network interface sends, to at least a given component of the multiple components, an indication specifying the corresponding operating frequency ranges used by one or more radio modules used for wireless communication with an access point. The given component determines whether an operating clock frequency of the given component overlaps any of the received operating frequency ranges and associated harmonic frequencies. If so, then the given component changes the operating clock frequency to a frequency that does not overlap any of the received operating frequency ranges and associated harmonic frequencies.

    LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT
    15.
    发明公开
    LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240319781A1

    公开(公告)日：2024-09-26

    申请号：US18189993

    申请日：2023-03-24

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Gia Tung Phan ,  Randall Brown ,  Ashish Jain

    IPC: G06F1/3234 ,  G06F1/3228 ,  G06F1/3287

    CPC classification number: G06F1/3275 ,  G06F1/3228 ,  G06F1/3287

    Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.

    PLATFORM EFFICIENCY TRACKER
    17.
    发明公开
    PLATFORM EFFICIENCY TRACKER 审中-公开

    公开(公告)号：US20240004448A1

    公开(公告)日：2024-01-04

    申请号：US17853759

    申请日：2022-06-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Eric D. Meyer ,  Austin Hung ,  Tianshu Liu

    IPC: G06F1/28 ,  G06F11/30

    CPC classification number: G06F1/28 ,  G06F11/3062

    Abstract: Systems, apparatuses, and methods for dynamically estimating power losses in a computing system. A system management circuit tracks a state of a computing system and dynamically estimates power losses in the computing system based in part on the state. Based on the estimated power losses, power consumption of the computing system is estimated. In response to detecting reduced power losses in at least a portion of the computing system, the system management circuit is configured to increase a power-performance state of one or more circuits of the computing system while remaining within a power allocation limit of the computing system.

    Performance State Selection for Low Activity Scenarios
    19.
    发明申请
    Performance State Selection for Low Activity Scenarios 有权
    低活动情景下的绩效状态选择

    公开(公告)号：US20160306406A1

    公开(公告)日：2016-10-20

    申请号：US14846058

    申请日：2015-09-04

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Alexander J. Branover ,  Adam N.C. Clark ,  Ashish Jain ,  Sridhar V. Gada

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20

    Abstract: A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.

    Abstract translation: 电力管理控制器跟踪计算单元的空闲状态，并将跟踪的空闲状态与第一阈值进行比较。 如果跟踪的空闲状态高于第一阈值，则计算单元的功率状态被限制为低功率状态，使得由于在低利用场景中发生的活动而导致功率状态不上升。 将跟踪的空闲状态与第二阈值进行比较，并且如果跟踪的空闲状态低于第二阈值，则指示计算单元不处于低利用率场景中，则去除功率状态的限制，并且计算的功率状态 单位被允许上升。

    DYNAMIC REALLOCATION OF DISPLAY MEMORY BANDWIDTH BASED ON SYSTEM STATE
    20.
    发明申请
    DYNAMIC REALLOCATION OF DISPLAY MEMORY BANDWIDTH BASED ON SYSTEM STATE 有权

    公开(公告)号：US20240403242A1

    公开(公告)日：2024-12-05

    申请号：US18327813

    申请日：2023-06-01

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Gia Tung Phan ,  Shang Yang

    IPC: G06F13/16 ,  G06F13/18

    Abstract: An apparatus and method for efficiently managing memory bandwidth within a communication fabric. A computing system includes multiple clients, a display controller, and a communication fabric that transfers data between the multiple clients, the display controller, and a memory subsystem. A control circuit with power management circuitry determines that one or more conditions are satisfied for changing a power-performance state (P-state) of the memory subsystem. The control circuit asserts indications on a sideband interface specifying to the communication fabric that the display controller is to have an increased bandwidth of data transfer between the display controller and the memory subsystem. Using the increased bandwidth provided by the communication fabric, the display controller prefetches display data from a frame buffer of the memory subsystem prior to the P-state change. Afterward, the memory subsystem performs the P-state change and the corresponding training of the memory interface.

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