公开(公告)号：US20230026633A1

公开(公告)日：2023-01-26

申请号：US17959925

申请日：2022-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shiu-Fang YEN ,  Chang-Lin YEH ,  Jen-Chieh KAO

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/38 ,  H01L25/065

Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

公开(公告)号：US20200161200A1

公开(公告)日：2020-05-21

申请号：US16751139

申请日：2020-01-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yi CHEN ,  Chang-Lin YEH ,  Jen-Chieh KAO

IPC: H01L23/31 ,  H01L23/498 ,  H01Q21/06 ,  H01L23/10 ,  H01Q1/22 ,  H01Q13/10 ,  H01L23/00 ,  H01Q19/10 ,  H01L23/66

Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.

公开(公告)号：US20250038136A1

公开(公告)日：2025-01-30

申请号：US18916604

申请日：2024-10-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Nan LIN ,  Wei-Tung CHANG ,  Jen-Chieh KAO ,  Huei-Shyong CHO

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01Q1/22 ,  H01Q1/24

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

公开(公告)号：US20200312733A1

公开(公告)日：2020-10-01

申请号：US16370633

申请日：2019-03-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Lin YEH ,  Jen-Chieh KAO ,  Sheng-Yu CHEN ,  Yu-Chang CHEN ,  Yu-Chang CHEN

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package structure includes a substrate having a first surface and a second surface opposite to the first surface; a first encapsulant disposed on the first surface of the substrate, and defining a cavity having a sidewall, wherein an accommodating space is defined by the sidewall of the cavity of the first encapsulant and the substrate, and the accommodating space has a volume capacity; and a connecting element disposed adjacent to the first surface of the substrate and in the cavity, wherein a volume of the connecting element is substantially equal to the volume capacity of the accommodating space.

公开(公告)号：US20180374805A1

公开(公告)日：2018-12-27

申请号：US16121467

申请日：2018-09-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Lin YEH ,  Jen-Chieh KAO ,  Chih-Yi HUANG ,  Fu-Chen CHU

IPC: H01L23/66 ,  H01L43/02 ,  H01L23/552

CPC classification number: H01L23/66 ,  H01L23/49838 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L43/02 ,  H01L2223/6605 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107

Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

公开(公告)号：US20180226365A1

公开(公告)日：2018-08-09

申请号：US15425723

申请日：2017-02-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Lin YEH ,  Jen-Chieh KAO ,  Chih-Yi HUANG ,  Fu-Chen CHU

IPC: H01L23/66 ,  H01L23/498 ,  H01L43/02

CPC classification number: H01L43/02 ,  H01L23/49838 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107

Abstract: A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first package body encapsulates the first surface of the substrate. The permeable element includes a first portion disposed on the first surface of the substrate and a second portion disposed on the package body. The coil is within the first package body.

公开(公告)号：US20180151485A1

公开(公告)日：2018-05-31

申请号：US15362548

申请日：2016-11-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jen-Chieh KAO ,  Chang-Lin YEH ,  Yi CHEN ,  Sung-Hung CHIANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/02 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/02 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/552 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16153 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012

Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.