公开(公告)号：US20160322292A1

公开(公告)日：2016-11-03

申请号：US15208569

申请日：2016-07-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang SU ,  Chih-Cheng LEE ,  Cheng-Lin HO

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

公开(公告)号：US20160133562A1

公开(公告)日：2016-05-12

申请号：US14703794

申请日：2015-05-04

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chih-Cheng LEE ,  Yuan-Chang SU ,  Yu-Lin SHIH ,  You-Lung Yen

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L21/481 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/92144

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.

Abstract translation: 本公开涉及一种半导体封装及其制造方法。 半导体封装包括封装层，封装层内的部件，第一介电层，第二介电层，第一图案化导电层和第二图案化导电层。 该部件包括在该部件的前表面上的焊盘。 第一介电层设置在封装层的表面上。 第二电介质层设置在第一电介质层的表面上。 第一和第二电介质层限定了从第二电介质层延伸到各个焊盘的通孔。 第一图案化导电层设置在第一介电层内并包围通孔。 第二图案化导电层设置在第二介电层内并包围通孔。

公开(公告)号：US20140367837A1

公开(公告)日：2014-12-18

申请号：US14303371

申请日：2014-06-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che LEE ,  Yuan-Chang SU ,  Wen-Chi CHENG ,  Guo-Cheng LIAO ,  Yi-Chuan DING

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Abstract translation: 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。