公开(公告)号：US20140367852A1

公开(公告)日：2014-12-18

申请号：US14304528

申请日：2014-06-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Yun-Hsiang TIEN ,  Yi-Chuan DING

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present disclosure provides a substrate and a semiconductor package. The substrate includes a body, at least one pad group, a plurality of traces and at least one pillar group. The pad group includes a plurality of pads. Each pad has at least one inner side and at least one outer side. The inner side of a first pad is faced to the inner side of an adjacent second pad with a spaced section between. Each pillar group includes a plurality of pillars disposed on respective ones of the pads. The use of pad groups having multiple pads on which to form pillars allows an increase in the number of the pillars available in a given area so as to increase the amount of I/O connections. Furthermore, for a given number of I/O connections, the area occupied by the pads, pillars and traces can be reduced.

摘要翻译： 本公开提供了一种基板和半导体封装。 衬底包括主体，至少一个衬垫组，多个迹线和至少一个支柱组。 垫组包括多个垫。 每个垫具有至少一个内侧和至少一个外侧。 第一垫的内侧面相邻的第二垫的内侧，其间具有间隔开的部分。 每个支柱组包括设置在各个垫上的多个支柱。 使用具有多个焊盘以形成支柱的焊盘组允许增加给定区域中可用的支柱数量，以增加I / O连接量。 此外，对于给定数量的I / O连接，可以减少由焊盘，柱和迹线占据的面积。

公开(公告)号：US20140367837A1

公开(公告)日：2014-12-18

申请号：US14303371

申请日：2014-06-12

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chun-Che LEE ,  Yuan-Chang SU ,  Wen-Chi CHENG ,  Guo-Cheng LIAO ,  Yi-Chuan DING

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

摘要： The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

摘要翻译： 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。

公开(公告)号：US20160336287A1

公开(公告)日：2016-11-17

申请号：US15222873

申请日：2016-07-28

申请人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.

发明人： Guo-Cheng LIAO ,  Chia-Ching CHEN ,  Yi-Chuan DING

IPC分类号： H01L23/00

CPC分类号： H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

摘要翻译： 半导体封装结构包括衬底，半导体芯片和焊料材料。 基板包括绝缘层，导电电路层和导电凸块。 导电电路层从绝缘层的顶表面凹入。 导电电路层包括焊盘，焊盘的侧表面沿绝缘层的侧表面延伸。 导电凸块设置在垫上。 导电凸块的侧表面，焊盘的顶表面和绝缘层的侧表面一起限定了容纳空间。 焊料材料电连接导电凸块和半导体芯片。 焊接材料的一部分设置在容纳空间中。

公开(公告)号：US20160190079A1

公开(公告)日：2016-06-30

申请号：US14586735

申请日：2014-12-30

申请人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.

发明人： Guo-Cheng LIAO ,  Chia-Ching CHEN ,  Yi-Chuan DING

IPC分类号： H01L23/00

CPC分类号： H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

摘要翻译： 本公开涉及包括半导体衬底，半导体芯片和导电材料的半导体封装结构。 半导体衬底包括绝缘层，导电电路层和导电凸块。 导电电路层从绝缘层的顶表面凹入，并且包括至少一个焊盘。 导电凸块设置在至少一个垫上。 导电凸块的侧表面，至少一个焊盘的顶表面和绝缘层的侧表面一起限定了容纳空间。 导电材料与导电凸块和半导体芯片电连接，导电材料的一部分设置在容纳空间中。