公开(公告)号：US11508655B2

公开(公告)日：2022-11-22

申请号：US16737817

申请日：2020-01-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Meng-Wei Hsieh ,  Teck-Chong Lee

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.

公开(公告)号：US10950531B2

公开(公告)日：2021-03-16

申请号：US16427193

申请日：2019-05-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683

Abstract: A semiconductor device package includes a first dielectric layer, a conductive pad and an electrical contact. The first dielectric layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed within the first dielectric layer. The conductive pad includes a first conductive layer and a barrier. The first conductive layer is adjacent to the second surface of the first dielectric layer. The first conductive layer has a first surface facing the first surface of the first dielectric layer and a second surface opposite to the first surface. The second surface of the first conductive layer is exposed from the first dielectric layer. The barrier layer is disposed on the first surface of the first conductive layer. The electrical contact is disposed on the second surface of the first conductive layer of the conductive pad.

公开(公告)号：US10861840B2

公开(公告)日：2020-12-08

申请号：US15691014

申请日：2017-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Teck-Chong Lee ,  Chien-Hua Chen

IPC: H01L27/01 ,  H01L49/02 ,  H01L21/683

Abstract: An integrated passive component comprises a capacitor, a first passivation layer, an inductor, an insulation layer and an external contact. The first passivation layer surrounds the capacitor. The inductor is on the first passivation layer and electrically connected to the capacitor. The inductor comprises a plurality of conductive pillars. The insulation layer is on the first passivation layer and surrounds each of the conductive pillars. The insulation layer comprises a first surface adjacent to the first passivation layer, a second surface opposite to the first surface, and a side surface extending between the first surface and the second surface. A ratio of a width of each of the conductive pillars to a height of each of the conductive pillars is about 1:7. The external contact is electrically connected to the inductor and contacts the second surface of the insulation layer and the side surface of the insulation layer.

公开(公告)号：US10241264B2

公开(公告)日：2019-03-26

申请号：US15201095

申请日：2016-07-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yi-Min Chin ,  Yung-Shun Chang ,  Mei-Ju Lu ,  Jia-Hao Zhang ,  Wen-Chi Hung

IPC: G02B6/36 ,  G02B6/12

Abstract: A semiconductor device package includes a substrate and an optical device. The optical device includes a first portion extending into the substrate and not extending beyond a first surface of the substrate. The optical device further includes a second portion extending along the first surface of the substrate.

公开(公告)号：US09929132B2

公开(公告)日：2018-03-27

申请号：US15406530

申请日：2017-01-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Teck-Chong Lee ,  Chien-Hua Chen ,  Yung-Shun Chang ,  Pao-Nan Lee

IPC: H01L27/08 ,  H01L27/01 ,  H01L49/02 ,  H01L23/528 ,  H01L21/70

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

公开(公告)号：US20170103946A1

公开(公告)日：2017-04-13

申请号：US15179683

申请日：2016-06-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun Chang ,  Chien-Hua Chen ,  Teck-Chong Lee

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/5227 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2021/60022 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81447 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and conductive vias. The at least one integrated passive device includes at least one capacitor disposed adjacent to a first surface of the substrate. The first redistribution layer is disposed adjacent to the first surface of the substrate. The second redistribution layer is disposed adjacent to a second surface of the substrate. The conductive vias extend through the substrate, and electrically connect the first redistribution layer and the second redistribution layer.

公开(公告)号：US09577027B2

公开(公告)日：2017-02-21

申请号：US14724522

申请日：2015-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Teck-Chong Lee ,  Chien-Hua Chen ,  Yung-Shun Chang ,  Pao-Nan Lee

IPC: H01L27/08 ,  H01L49/02 ,  H01L27/01 ,  H01L21/768 ,  H01L21/48 ,  H05K1/03 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L27/016 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/707 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/528 ,  H01L28/10 ,  H01L28/60 ,  H01L2224/4813 ,  H05K1/0306 ,  H05K1/185 ,  H05K2201/0154

Abstract: A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

Abstract translation: 半导体器件包括衬底，种子层，第一图案化金属层，电介质层和第二金属层。 种子层设置在基板的表面上。 第一图案化金属层设置在种子层上并具有第一厚度。 第一图案化金属层包括第一部分和第二部分。 电介质层设置在第一图案化金属层的第一部分上。 第二金属层设置在电介质层上，具有第二厚度，其中第一厚度大于第二厚度。 第一图案化金属层的第一部分，电介质层和第二金属层形成电容器。 第一图案化金属层的第一部分是电容器的下电极，第一图案化金属层的第二部分是电感器。