公开(公告)号：US07960036B2

公开(公告)日：2011-06-14

申请号：US11831005

申请日：2007-07-31

申请人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

发明人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

IPC分类号： B32B9/00 ,  B32B19/00 ,  B32B15/04

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

公开(公告)号：US20110042771A1

公开(公告)日：2011-02-24

申请号：US12542970

申请日：2009-08-18

申请人： Wu-Song Huang ,  Martin Glodde ,  Dario L. Goldfarb ,  Wai-Kin Li ,  Sen Liu ,  Libor Vyklicky

发明人： Wu-Song Huang ,  Martin Glodde ,  Dario L. Goldfarb ,  Wai-Kin Li ,  Sen Liu ,  Libor Vyklicky

IPC分类号： H01L31/0216 ,  G03F7/004 ,  G03F7/20

CPC分类号： G03F7/0388 ,  G03F7/038 ,  G03F7/091 ,  G03F7/11 ,  H01L51/447

摘要： A curable liquid formulation comprising: (i) one or more near-infrared absorbing polymethine dyes; (ii) one or more crosslinkable polymers; and (iii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film.

摘要翻译： 一种可固化液体制剂，其包含：（i）一种或多种近红外吸收聚甲炔染料; （ii）一种或多种可交联聚合物; 和（iii）一种或多种浇铸溶剂。 本发明还涉及由可固化液体制剂的交联形式组成的固体近红外吸收膜。 本发明还涉及一种含有固体近红外线吸收膜的涂层的微电子衬底，以及在近红外吸收膜位于微电子衬底之间的情况下，用于图案化涂覆在微电子衬底上的光刻胶层的方法 和光刻胶膜。

公开(公告)号：US07803521B2

公开(公告)日：2010-09-28

申请号：US11942062

申请日：2007-11-19

申请人： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-Kin Li ,  Pushkara R. Varanasi

发明人： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-Kin Li ,  Pushkara R. Varanasi

IPC分类号： G03F7/30

CPC分类号： G03F7/0048 ,  G03F7/0035 ,  G03F7/0397 ,  G03F7/40

摘要： A photoresist composition and methods using the photoresist composition in multiple exposure/multiple layer processes. The photoresist composition includes a polymer comprising repeat units having a hydroxyl moiety; a photoacid generator; and a solvent. The polymer when formed on a substrate is substantially insoluble to the solvent after heating to a temperature of about 150° C. or greater. One method includes forming a first photoresist layer on a substrate, patternwise exposing the first photoresist layer, forming a second non photoresist layer on the substrate and patterned first photoresist layer. Another method includes forming a first photoresist layer on a substrate, patternwise exposing the first photoresist layer, forming a second photoresist layer on the substrate and patterned first photoresist layer and patternwise exposing the second photoresist layer.

摘要翻译： 光致抗蚀剂组合物和在多次曝光/多层工艺中使用光致抗蚀剂组合物的方法。 光致抗蚀剂组合物包括包含具有羟基部分的重复单元的聚合物; 光致酸发生器; 和溶剂。 形成在基材上的聚合物在加热至约150℃或更高的温度之后基本上不溶于溶剂。 一种方法包括在衬底上形成第一光致抗蚀剂层，图案地暴露第一光致抗蚀剂层，在衬底上形成第二非光致抗蚀剂层并且形成图案化的第一光致抗蚀剂层。 另一种方法包括在衬底上形成第一光致抗蚀剂层，以图形方式暴露第一光致抗蚀剂层，在衬底上形成第二光致抗蚀剂层并图案化的第一光致抗蚀剂层和图案地曝光第二光致抗蚀剂层。

公开(公告)号：US20100209853A1

公开(公告)日：2010-08-19

申请号：US12371956

申请日：2009-02-17

申请人： Kuang-Jung Chen ,  Wai-Kin Li

发明人： Kuang-Jung Chen ,  Wai-Kin Li

IPC分类号： G03F7/26

CPC分类号： G03F7/40 ,  G03F7/0035

摘要： A method forms a first patterned mask (comprising rectangular features and/or rounded openings) on a planar surface and forms a second patterned mask on the first patterned mask and the planar surface. The second patterned mask covers protected portions of the first patterned mask and the second patterned mask reveals exposed portions of the first patterned mask. The method treats the exposed portions of the first patterned mask with a chemical treatment that reduces the size of the exposed portions to create an altered first patterned mask.

摘要翻译： 一种方法在平坦表面上形成第一图案化掩模（包括矩形特征和/或圆形开口）并且在第一图案化掩模和平面表面上形成第二图案化掩模。 第二图案化掩模覆盖第一图案化掩模的受保护部分，并且第二图案化掩模揭示第一图案化掩模的暴露部分。 该方法通过减少暴露部分的尺寸以产生改变的第一图案化掩模的化学处理来处理第一图案化掩模的暴露部分。

公开(公告)号：US20100009298A1

公开(公告)日：2010-01-14

申请号：US12170722

申请日：2008-07-10

申请人： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-Kin Li

发明人： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-Kin Li

IPC分类号： G03F7/20

CPC分类号： G03F7/2024

摘要： Methods are presented of forming sub-lithographic patterns using double exposure. One method may include providing a photoresist layer over a layer to be patterned; exposing the photoresist layer using a first mask having a first opening; developing the photoresist layer to transfer the first opening into the photoresist layer, forming a boundary in the photoresist layer about the transferred first opening that is hardened; exposing the photoresist layer using a second mask having a second opening that overlaps the boundary; and developing the photoresist layer to transfer the second opening into the photoresist layer, leaving the boundary, wherein the boundary has a sub-lithographic dimension.

摘要翻译： 提出了使用双重曝光形成亚光刻图案的方法。 一种方法可以包括在待图案化的层上提供光致抗蚀剂层; 使用具有第一开口的第一掩模曝光光致抗蚀剂层; 显影所述光致抗蚀剂层以将所述第一开口转移到所述光致抗蚀剂层中，在所述光致抗蚀剂层周围形成围绕被硬化的转移的第一开口的边界; 使用具有与边界重叠的第二开口的第二掩模曝光光致抗蚀剂层; 并且显影所述光致抗蚀剂层以将所述第二开口转移到所述光致抗蚀剂层中，留下所述边界，其中所述边界具有亚光刻尺寸。

公开(公告)号：US07560222B2

公开(公告)日：2009-07-14

申请号：US11554877

申请日：2006-10-31

申请人： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-Kin Li ,  Yi-Hsiung S. Lin

发明人： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-Kin Li ,  Yi-Hsiung S. Lin

IPC分类号： G03F7/36 ,  G03F7/34

CPC分类号： G03F7/0758 ,  G03F7/0045

摘要： A resist polymer that has nano-scale patterns located therein that are in the form of sub lithographic hollow pores (or openings) that are oriented in a direction that is substantially perpendicular with that of its major surfaces (top and bottom) is provided. Such a resist polymer having the nano-scale patterns is used as an etch mask transferring nano-scale patterns to an underlying substrate such as, for example, dielectric material. After the transferring of the nano-scale patterns into the substrate, nano-scale voids (or openings) having a width of less than 50 nm are created in the substrate. The presence of the nano-scale voids in a dielectric material lowers the dielectric constant, k, of the original dielectric material. In accordance with an aspect of the present invention, the inventive resist polymer comprises a copolymer that includes a first monomer unit (A) that contains a Si-containing component, and a second monomer unit (B) that contains an organic component, wherein said two monomer units (A and B) have different etch rates.

摘要翻译： 提供具有位于其中的纳米级图案的抗蚀剂聚合物，其为沿与其主表面（顶部和底部）基本垂直的方向取向的亚光刻中空孔（或开口）的形式。 具有纳米尺度图案的这种抗蚀剂聚合物被用作将纳米尺度图案转移到诸如介电材料的下层基底的蚀刻掩模。 在将纳米尺度图案转移到基底中之后，在基底中产生宽度小于50nm的纳米级空隙（或开口）。 电介质材料中纳米尺度空隙的存在降低了原始电介质材料的介电常数k。 根据本发明的一个方面，本发明的抗蚀剂聚合物包括包含含有含Si组分的第一单体单元（A）和含有有机组分的第二单体单元（B）的共聚物，其中所述 两个单体单元（A和B）具有不同的蚀刻速率。

公开(公告)号：US20090045484A1

公开(公告)日：2009-02-19

申请号：US11839716

申请日：2007-08-16

申请人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

IPC分类号： H01L23/52 ,  H01H37/76 ,  H01L23/525 ,  H01L21/44 ,  H01L29/00

CPC分类号： G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

摘要翻译： 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。

公开(公告)号：US07485567B2

公开(公告)日：2009-02-03

申请号：US11670524

申请日：2007-02-02

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificial material over the first wiring level; and forming a plurality of interconnect openings and a plurality of gap openings in the alternating layers of layer dielectric material and sacrificial material. The interconnect openings are formed over the first wiring level conductors. The method further includes forming (i) metallic conductors comprising second wiring level conductors, and (ii) interconnects, at the interconnect openings; and removing the layers of the sacrificial material through the gap openings.

摘要翻译： 一种制造微电子电路的方法包括以下步骤：提供包括由第一布线层介电材料隔开的第一布线层导体的第一布线层; 在所述第一布线层上形成层状介电材料和牺牲材料的多个交替层; 以及在层介电材料和牺牲材料的交替层中形成多个互连开口和多个间隙开口。 互连开口形成在第一布线层导体上。 该方法还包括形成（i）包括第二布线层导体的金属导体，和（ii）互连开口处的互连; 并且通过间隙开口去除牺牲材料的层。

公开(公告)号：US07482270B2

公开(公告)日：2009-01-27

申请号：US11566848

申请日：2006-12-05

申请人： Wai-Kin Li ,  Haining Yang

发明人： Wai-Kin Li ,  Haining Yang

IPC分类号： H01L21/44

CPC分类号： H01L29/42316 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  Y10S977/892

摘要： Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

摘要翻译： 通过用亚光刻，亚临界尺寸，纳米级开口深度“穿孔”硅化物栅极导体，产生完全均匀的硅化栅极导体。 然后沉积硅化物形成金属（例如钴，钨等），覆盖它们并填充穿孔的多晶硅栅极。 退火步骤将多晶硅转化为硅化物。 由于深的穿孔，与硅化物形成金属接触的多晶硅的表面积比常规硅化技术大大增加，导致多晶硅栅极被完全转变成均匀的硅化物组成。 使用自组装二嵌段共聚物来形成用作形成穿孔的蚀刻“模板”的规则的亚光刻纳米尺度图案。

公开(公告)号：US20080303164A1

公开(公告)日：2008-12-11

申请号：US11758206

申请日：2007-06-05

申请人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chandra ,  Ronald G. Filippi ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

摘要翻译： 用于减少半导体器件中的电迁移破裂和挤出效应的结构包括形成在第一介电层中的第一金属线; 形成在第一金属线和第一介电层上的盖层; 形成在所述盖层上的第二电介质层; 以及形成在第二介电层中的空隙，停止在盖层上，其中，空隙以如下方式定位，以便隔离由于第一金属线的电迁移效应引起的结构损坏，包括一种或多种金属挤压的效果 来自第一金属线的材料和帽层相对于第一介电层分层的裂纹。