公开(公告)号：US20240072806A1

公开(公告)日：2024-02-29

申请号：US18214947

申请日：2023-06-27

Applicant: Ambiq Micro, Inc.

Inventor： Scott Hanson ,  Daniel Martin Cermak

IPC: H03K19/17784 ,  H03K19/173 ,  H03K19/1776

CPC classification number: H03K19/17784 ,  H03K19/1737 ,  H03K19/1776

Abstract: Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.

公开(公告)号：US20230376222A1

公开(公告)日：2023-11-23

申请号：US17981149

申请日：2022-11-04

Applicant: Ambiq Micro, Inc.

Inventor： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

Abstract: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

公开(公告)号：US11689204B1

公开(公告)日：2023-06-27

申请号：US17894023

申请日：2022-08-23

Applicant: Ambiq Micro, Inc.

Inventor： Scott Hanson ,  Daniel Martin Cermak

IPC: H03K19/17784 ,  H03K19/173 ,  H03K19/1776

CPC classification number: H03K19/17784 ,  H03K19/1737 ,  H03K19/1776

Abstract: Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.

公开(公告)号：US20230148253A1

公开(公告)日：2023-05-11

申请号：US18053610

申请日：2022-11-08

Applicant: Ambiq Micro, Inc.

Inventor： Daniel Martin Cermak ,  Stephen James Sheafor

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679

Abstract: A low power caching architecture is disclosed. The architecture includes multiple data memory regions, each including a cache memory. The data memory regions are coupled to a peripheral device. A host processor is operable to control power to each of the plurality of data memory regions. The host processor is operable to power on any of data memory regions and power down any unused data memory regions of the data memory regions. A cache control logic is operable to receive a data request from the host processor. The cache control logic requests the data from the peripheral. The host processor powers on at least one of the data memory regions, and stores the requested data in the cache memory of the powered on data memory region.

公开(公告)号：US11520499B1

公开(公告)日：2022-12-06

申请号：US17747410

申请日：2022-05-18

Applicant: Ambiq Micro, Inc.

Inventor： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

IPC: G06F3/06

Abstract: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

公开(公告)号：US20190079575A1

公开(公告)日：2019-03-14

申请号：US16013767

申请日：2018-06-20

Applicant: Ambiq Micro, Inc.

Inventor： Scott McLean Hanson ,  Daniel Martin Cermak ,  Eric Jonathan Deal ,  Stephen James Sheafor ,  Donovan Scott Popps ,  Mark A. Baur

IPC: G06F1/32

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

公开(公告)号：US20190079574A1

公开(公告)日：2019-03-14

申请号：US16005315

申请日：2018-06-11

Applicant: Ambiq Micro, Inc.

Inventor： Scott McLean Hanson ,  Daniel Martin Cermak ,  Eric Jonathan Deal ,  Stephen James Sheafor ,  Donovan Scott Popps ,  Mark A. Baur

IPC: G06F1/32

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.