公开(公告)号：US09943266B2

公开(公告)日：2018-04-17

申请号：US14972368

申请日：2015-12-17

Applicant: ANALOG DEVICES, INC.

Inventor： Robert Adams ,  Sefa Demirtas ,  Jeffrey G. Bernstein

IPC: A61B5/02 ,  A61B5/00 ,  A61B5/024 ,  A61B5/11

CPC classification number: A61B5/721 ,  A61B5/02416 ,  A61B5/02438 ,  A61B5/11 ,  A61B5/725 ,  A61B5/7275 ,  A61B2562/0219 ,  A61B2562/0233 ,  G06F19/00

Abstract: Heart rate monitors are plagued by noisy photoplethysmography (PPG) data, which makes it difficult for the monitors to output a consistently accurate heart rate reading. Noise is often caused by motion. Using known methods for processing accelerometer readings that measure movement to filter out some of this noise may help, but not always. The present disclosure describes an improved front-end technique (time-domain interference removal) based on using adaptive linear prediction on accelerometer data to generate filters for filtering the PPG signal prior to tracking the frequency of the heartbeat (heart rate). The present disclosure also describes an improved back-end technique based on steering the frequency of a resonant filter in order to track the heartbeat. Implementing one or both of these techniques leads to more accurate heart rate measurements.

公开(公告)号：US20220156219A1

公开(公告)日：2022-05-19

申请号：US17589715

申请日：2022-01-31

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Miguel A. CHAVEZ ,  Lewis F. LAHR ,  William HOOPER ,  Robert Adams ,  Peter SEALEY

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US11238004B2

公开(公告)日：2022-02-01

申请号：US16859611

申请日：2020-04-27

Applicant: Analog Devices, Inc.

Inventor： Martin Kessler ,  Miguel A. Chavez ,  Lewis F. Lahr ,  William Hooper ,  Robert Adams ,  Peter Sealey

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364 ,  H04R29/00

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.