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59 条记录 (耗时 0.028 秒)

    Method and apparatus for integrating multiple process controllers
    12.
    发明授权
    Method and apparatus for integrating multiple process controllers 失效
    用于集成多个过程控制器的方法和设备

    公开(公告)号：US06801817B1

    公开(公告)日：2004-10-05

    申请号：US09789140

    申请日：2001-02-20

    申请人： Christopher A. Bode ,  Alexander J. Pasadyn ,  Anthony J. Toprac ,  Joyce S. Oey Hewett ,  Anastasia Oshelski Peterson ,  Thomas J. Sonderman ,  Michael L. Miller

    发明人： Christopher A. Bode ,  Alexander J. Pasadyn ,  Anthony J. Toprac ,  Joyce S. Oey Hewett ,  Anastasia Oshelski Peterson ,  Thomas J. Sonderman ,  Michael L. Miller

    IPC分类号： G06F1900

    CPC分类号： G05B19/41865 ,  G05B19/40937 ,  Y02P90/16 ,  Y02P90/20 ,  Y02P90/265

    摘要： A method for controlling a manufacturing system includes processing workpieces in a plurality of tools; initiating a baseline control script for a selected tool of the plurality of tools; providing context information for the baseline control script; determining a tool type based on the context information; selecting a group of control routines for the selected tool based on the tool type; determining required control routines from the group of control routines based on the context information; and executing the required control routines to generate control actions for the selected tool. A manufacturing system includes a plurality of tools adapted to process workpieces, a control execution manager, and a control executor. The control execution manager is adapted to initiate a baseline control script for a selected tool of the plurality of tools and provide context information for the baseline control script. The control executor is adapted to execute the baseline control script, determine a tool type based on the context information, select a group of control routines for the selected tool based on the tool type, determine required control routines from the group of control routines based on the context information, and execute the required control routines to generate control actions for the selected tool.

    摘要翻译： 一种用于控制制造系统的方法包括：处理多个工具中的工件; 为所述多个工具的所选择的工具启动基线控制脚本; 提供基线控制脚本的上下文信息; 基于上下文信息确定工具类型; 基于所述工具类型为所选择的工具选择一组控制例程; 基于所述上下文信息来确定来自所述一组控制例程的所需控制例程; 并执行所需的控制例程以产生所选择的工具的控制动作。 制造系统包括适于处理工件的多个工具，控制执行管理器和控制执行器。 所述控制执行管理器适于启动用于所述多个工具的所选工具的基线控制脚本并提供所述基线控制脚本的上下文信息。 控制执行器适于执行基线控制脚本，基于上下文信息确定工具类型，基于工具类型为所选择的工具选择一组控制例程，从基于控制例程的组中确定所需的控制例程 上下文信息，并执行所需的控制例程以生成所选择的工具的控制动作。

    Method and apparatus for automatic routing for reentrant processes
    14.
    发明授权
    Method and apparatus for automatic routing for reentrant processes 有权
    用于可重入流程的自动路由的方法和装置

    公开(公告)号：US06529789B1

    公开(公告)日：2003-03-04

    申请号：US10097467

    申请日：2002-03-14

    申请人： William Jarrett Campbell ,  Anthony J. Toprac ,  Christopher A. Bone

    发明人： William Jarrett Campbell ,  Anthony J. Toprac ,  Christopher A. Bone

    IPC分类号： G06F1900

    CPC分类号： G05B19/41865 ,  G05B2219/32265 ,  G05B2219/32324 ,  G05B2219/45031 ,  H01L21/67276 ,  Y02P90/20

    摘要： The present invention provides for a method and an apparatus for automatic routing of semiconductor devices within a manufacturing area. Performance of a plurality of manufacturing tools is tracked while processing semiconductor devices. At least one optimal combination of the manufacturing tools is determined based upon the tracked performance of the manufacturing tools. A queuing system is implemented to attain the optimal combination of the manufacturing tools. A dispatch system is deployed in response to the queuing system for routing the semiconductor devices within the manufacturing area.

    摘要翻译： 本发明提供一种用于在制造区域内自动路由半导体器件的方法和装置。 在处理半导体器件的同时跟踪多个制造工具的性能。 基于制造工具的跟踪性能来确定制造工具的至少一个最佳组合。 实施排队系统以实现制造工具的最佳组合。 响应于用于在制造区域内布线半导体器件的排队系统部署调度系统。

    Method and apparatus for run-to-run controlling of overlay registration
    15.
    发明授权
    Method and apparatus for run-to-run controlling of overlay registration 有权
    覆盖登记的运行控制方法和装置

    公开(公告)号：US06405096B1

    公开(公告)日：2002-06-11

    申请号：US09371550

    申请日：1999-08-10

    申请人： Anthony J. Toprac ,  Christopher A. Bode ,  Richard D. Edwards

    发明人： Anthony J. Toprac ,  Christopher A. Bode ,  Richard D. Edwards

    IPC分类号： G06F1900

    CPC分类号： G03F7/70633 ,  H01L22/20

    摘要： The present invention provides for a method and apparatus for correction of overlay control errors. Semiconductor devices are processed based upon control input parameters. The processed semiconductor devices are examined in a review station. The control input parameters are modified in response to the examination of the processed semiconductor devices. New control input parameters are implemented for a subsequent run of the semiconductor device processing step based upon the modification of the control input parameters.

    摘要翻译： 本发明提供了一种用于校正重叠控制误差的方法和装置。 基于控制输入参数来处理半导体器件。 处理的半导体器件在检查站中进行检查。 响应于对被处理的半导体器件的检查，修改控制输入参数。 基于控制输入参数的修改，实现新的控制输入参数用于随后的半导体器件处理步骤的运行。

    Method of controlling feature dimensions based upon etch chemistry concentrations
    16.
    发明授权
    Method of controlling feature dimensions based upon etch chemistry concentrations 有权
    基于蚀刻化学浓度控制特征尺寸的方法

    公开(公告)号：US06352867B1

    公开(公告)日：2002-03-05

    申请号：US09478181

    申请日：2000-01-05

    申请人： Terri A. Couteau ,  William Jarrett Campbell ,  Anthony J. Toprac

    发明人： Terri A. Couteau ,  William Jarrett Campbell ,  Anthony J. Toprac

    IPC分类号： H01L2100

    CPC分类号： H01L21/32134

    摘要： The present invention is directed to a method of controlling the width of a gate electrode based upon the etch rate of a chemical bath. In one illustrative embodiment, the method comprises determining an etching rate for a chemical bath, determining the manufactured width of the gate electrode, and varying the time duration of an etching process performed in the bath depending upon the etch rate of the bath and the width of the gate electrode.

    摘要翻译： 本发明涉及一种基于化学浴蚀刻速率来控制栅电极的宽度的方法。 在一个说明性实施例中，该方法包括确定用于化学浴的蚀刻速率，确定制造的栅电极的宽度，并且根据镀液的蚀刻速率和宽度来改变在镀液中进行的蚀刻工艺的持续时间 的栅电极。

    Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements
    17.
    发明授权
    Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements 失效
    基于独立临界尺寸测量来表征半导体器件性能变化的方法和装置

    公开(公告)号：US06346426B1

    公开(公告)日：2002-02-12

    申请号：US09716181

    申请日：2000-11-17

    申请人： Anthony J. Toprac ,  Derick J. Wristers ,  Jon D. Cheek

    发明人： Anthony J. Toprac ,  Derick J. Wristers ,  Jon D. Cheek

    IPC分类号： H01L2100

    CPC分类号： H01L22/26 ,  H01L22/12

    摘要： A method for characterizing semiconductor device performance variations includes processing a wafer in a processing line to form a feature on the wafer; measuring a physical critical dimension of the feature in a first metrology tool to generate a first critical dimension measurement; measuring the physical critical dimension of the feature in a second metrology tool to generate a second critical dimension measurement independent of the first critical dimension measurement; determining an effective critical dimension of the feature in a third metrology tool to generate a third critical dimension measurement; and comparing the first, second, and third critical dimension measurements to identify a metrology drift in one of the first and second metrology tools. A system for characterizing semiconductor device performance variations includes a processing line, first, second, and third metrology tools, and a process controller. The processing line is adapted to process a wafer to form a feature on the wafer. The first metrology tool is adapted to measure a physical critical dimension of the feature to generate a first critical dimension measurement. The second metrology tool is adapted to measure the physical critical dimension of the feature to generate a second critical dimension measurement independent of the first critical dimension measurement. The third metrology tool adapted to determine an effective critical dimension of the feature to generate a third critical dimension measurement. The process controller is adapted to compare the first, second, and third critical dimension measurements to identify a metrology drift in one of the first and second metrology tools.

    摘要翻译： 用于表征半导体器件性能变化的方法包括处理处理线中的晶片以在晶片上形成特征; 测量第一计量工具中的特征的物理临界尺寸以产生第一临界尺寸测量; 在第二计量工具中测量所述特征的物理临界尺寸以产生独立于所述第一临界尺寸测量的第二临界尺寸测量; 确定第三计量工具中的特征的有效临界尺寸以产生第三临界尺寸测量; 以及比较所述第一，第二和第三临界尺寸测量值以识别所述第一和第二测量工具之一中的度量漂移。 用于表征半导体器件性能变化的系统包括处理线，第一，第二和第三计量工具以及过程控制器。 处理线适于处理晶片以在晶片上形成特征。 第一计量工具适用于测量特征的物理关键尺寸以产生第一临界尺寸测量。 第二计量工具适于测量特征的物理临界尺寸以产生独立于第一临界尺寸测量的第二临界尺寸测量。 第三计量工具适于确定特征的有效临界尺寸以产生第三临界尺寸测量。 过程控制器适于比较第一，第二和第三关键尺寸测量值以识别第一和第二计量工具之一中的度量漂移。

    Forced-flow wafer polisher
    19.
    发明授权
    Forced-flow wafer polisher 失效
    强制流动晶片抛光机

    公开(公告)号：US5783497A

    公开(公告)日：1998-07-21

    申请号：US284316

    申请日：1994-08-02

    申请人： Scott Runnels ,  Anthony J. Toprac

    发明人： Scott Runnels ,  Anthony J. Toprac

    IPC分类号： H01L21/3105 ,  H01L21/321 ,  H01L21/00

    CPC分类号： H01L21/31053 ,  H01L21/3212

    摘要： A forced-flow polishing technique forcibly flows slurry across the surface of a wafer. The slurry and the wafer are contained in a confined space so that the slurry flow is between a fixed upper and lower boundaries. The slurry flow places selective stress on wafer features such that taller surfaces are eroded at a faster rate. The constant flow allows for uniformity in achieving the selective erosion across the wafer surface.

    摘要翻译： 强制流动抛光技术强制地将浆料流过晶片的表面。 浆料和晶片被包含在密闭空间中，使得浆料流在固定的上边界和下边界之间。 浆料流将选择性应力放置在晶片特征上，使得较高的表面以更快的速率被侵蚀。 恒定流量允许在晶片表面上实现选择性腐蚀的均匀性。

    Method for chemical-mechanical polish control in semiconductor manufacturing
    20.
    发明授权
    Method for chemical-mechanical polish control in semiconductor manufacturing 有权
    半导体制造中化学机械抛光控制方法

    公开(公告)号：US06884147B2

    公开(公告)日：2005-04-26

    申请号：US10401336

    申请日：2003-03-28

    申请人： Anthony J. Toprac

    发明人： Anthony J. Toprac

    IPC分类号： B24B37/04 ,  B24D13/14 ,  H01L21/306 ,  B24B1/00

    CPC分类号： B24D13/147 ,  B24B37/042 ,  B24D2203/00 ,  H01L21/30625

    摘要： A method for planarizing the surface of a semiconductor wafer or device during manufacture. Dependencies of polish rate and substrate thickness on process parameters of downforce and polish speed, and on the characteristic product high feature area on the wafer, are explicitly defined and used to control Chemical-Mechanical Polish in Run-to-Run and real-time semiconductor production control applications.

    摘要翻译： 一种用于在制造期间平面化半导体晶片或器件的表面的方法。 抛光速率和衬底厚度对下压力和抛光速度的工艺参数的依赖性以及晶片上特征性产品高特征区域的明确定义并用于控制运行中的化学机械抛光和实时半导体 生产控制应用。