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公开(公告)号：US20170277245A1
公开(公告)日：2017-09-28
申请号：US15219984
申请日：2016-07-26
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Eran Sandel , Lior Mouler , Liran Erez , Matthew J. Byom , Muhammad N. Ashraf , Roman Guy
CPC classification number: G06F1/3275 , G06F1/263 , G06F1/30 , G06F1/3287 , G06F11/00
Abstract: Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.
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公开(公告)号：US09361036B2
公开(公告)日：2016-06-07
申请号：US14754468
申请日：2015-06-29
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Daniel J. Post
CPC classification number: G06F3/0619 , G06F3/0631 , G06F3/0679 , G06F11/1004 , G06F11/1008 , G06F11/1048
Abstract: Systems and methods are disclosed for correcting block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This enables a space efficient approach for recovering from single-block data errors.
Abstract translation: 公开了用于校正块错误的系统和方法。 特别地，系统可以每页模数地存储奇偶校验页，其中可以将NVM的块或带的预定数量的页分配为页模XOR（“PMX”）奇偶页。 这实现了从单块数据错误中恢复的空间有效的方法。
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13.发明申请公开(公告)号：US20150301760A1
公开(公告)日：2015-10-22
申请号：US14754468
申请日：2015-06-29
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Daniel J. Post
CPC classification number: G06F3/0619 , G06F3/0631 , G06F3/0679 , G06F11/1004 , G06F11/1008 , G06F11/1048
Abstract: Systems and methods are disclosed for correction of block errors for a system having non-volatile memory (“NVM”). In particular, the system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.
Abstract translation: 公开了用于校正具有非易失性存储器（“NVM”）的系统的块错误的系统和方法。 特别地，系统可以每页模数地存储奇偶校验页，其中可以将NVM的块或带的预定数量的页分配为页模XOR（“PMX”）奇偶校验页。 这可以是用于从单块数据错误（例如，单页不可校正纠错码（“uECC”））和/或由字线短路引起的错误进行恢复的空间有效的方法。
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公开(公告)号：US08990614B2
公开(公告)日：2015-03-24
申请号：US13829692
申请日：2013-03-14
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Daniel J. Post
CPC classification number: G06F11/1666 , G06F11/073 , G06F11/1068 , G06F12/0246 , G11C29/808 , G11C29/82
Abstract: Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region.
Abstract translation: 公开了用于改善具有非易失性存储器（“NVM”）的系统的性能的系统和方法。 该系统可以垂直地将NVM的用户区域的缺陷块重新向量到具有相同平面或管芯平面（“DIP”）但对应于NVM的死区的其他块。 然后，系统可以选择具有多于一个缺陷块的任何频带，并将其缺陷块中的一个垂直重新矢量到没有有缺陷块的频带。 在运行时，系统可以监控每个DIP的垂直重新向量的数量。 如果在NVM的所有DIP上执行了至少一个垂直重新向量，则可以为死区分配用户区域的频带。
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公开(公告)号：US20140281814A1
公开(公告)日：2014-09-18
申请号：US13829088
申请日：2013-03-14
Applicant: APPLE INC.
Inventor： Andrew W. Vogan , Daniel J. Post
IPC: G06F11/10
CPC classification number: G06F3/0619 , G06F3/0631 , G06F3/0679 , G06F11/1004 , G06F11/1008 , G06F11/1048
Abstract: Systems and methods are disclosed for correction of block errors for a system having non-volatile memory (“NVM”). In particular, the system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.
Abstract translation: 公开了用于校正具有非易失性存储器（“NVM”）的系统的块错误的系统和方法。 特别地，系统可以每页模数地存储奇偶校验页，其中可以将NVM的块或带的预定数量的页分配为页模XOR（“PMX”）奇偶校验页。 这可以是用于从单块数据错误（例如，单页不可校正纠错码（“uECC”））和/或由字线短路引起的错误进行恢复的空间有效的方法。
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Patent Agency Ranking
公开(公告)号：US11579789B2
公开(公告)日：2023-02-14
申请号：US15721081
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan
Abstract: Disclosed herein are techniques for managing context information for data stored within a non-volatile memory of a computing device. According to some embodiments, the method can include (1) loading, into a volatile memory of the computing device, the context information from the non-volatile memory, where the context information is separated into a plurality of silos, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: (i) identifying a next silo of the plurality of silos to be written into the non-volatile memory, (ii) updating the next silo to reflect the transactions that apply to the next silo, and (iii) writing the next silo into the non-volatile memory. In turn, when an inadvertent shutdown of the computing device occurs, the silos of which the context information is comprised can be sequentially accessed and restored in an efficient manner.
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17.发明授权公开(公告)号：US11288184B2
公开(公告)日：2022-03-29
申请号：US17131698
申请日：2020-12-22
Applicant: Apple Inc.
Inventor： Andrew W. Vogan
Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein define a native logical space to manage relatively high volume data write operations and define an artificially limited logical space to manage relatively low volume data write operations. The native logical space may include native logical bands that are mapped to a native number of physical blocks to enable high volume, high data transfer of data. The artificially limited logical space may include artificially limited logical bands that are mapped to an artificially limited number of available physical blocks. The artificially limited logical bands are better suited for low volume, low data transfer of data and do not unnecessarily tie up a native number of physical blocks.
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公开(公告)号：US11256436B2
公开(公告)日：2022-02-22
申请号：US16277230
申请日：2019-02-15
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan
IPC: G06F3/06
Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
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公开(公告)号：US20180121131A1
公开(公告)日：2018-05-03
申请号：US15854299
申请日：2017-12-26
Applicant: Apple Inc.
Inventor： Andrew W. Vogan , Charan Srinivasan , Matthew J. Byom
IPC: G06F3/06
CPC classification number: G06F3/0647 , G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: Systems and methods for managing data in non-volatile memory devices across a large range of operating temperatures are provided. Embodiments discussed herein selectively reprogram previously programmed data at a temperature that better enables the data to be read regardless of where within the range of operating temperatures the data is being read. Circuitry and methods discussed herein can keep track of a program temperature associated with each portion of non-volatile memory and use this information along with other criteria to selectively perform temperature based moves of data. This enables a mechanism for data to programmed in out-of-bounds temperature ranges to be reprogrammed within an in-bounds temperatures range so that a temperature delta between the reprogrammed temperature and the read operation temperature is below a threshold that ensure efficient and error free read operations to be performed.
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公开(公告)号：US09772959B2
公开(公告)日：2017-09-26
申请号：US14292123
申请日：2014-05-30
Applicant: Apple Inc.
Inventor： Russell A. Blaine , Kushal Dalmia , Joseph Sokol, Jr. , Andrew W. Vogan , Matthew J. Byom
CPC classification number: G06F13/18 , G06F3/0611 , G06F3/0659 , G06F3/0688 , G06F9/00 , G06F13/385
Abstract: In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request.
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