公开(公告)号：US12242855B2

公开(公告)日：2025-03-04

申请号：US18361212

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US20240036870A1

公开(公告)日：2024-02-01

申请号：US18361212

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/3814 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3877 ,  G06F9/4881 ,  G06F9/522

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US20200371812A1

公开(公告)日：2020-11-26

申请号：US16991858

申请日：2020-08-12

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta

IPC: G06F9/38 ,  G06F12/0815 ,  G06F12/084

Abstract: In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.

公开(公告)号：US20200183736A1

公开(公告)日：2020-06-11

申请号：US16210231

申请日：2018-12-05

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0815

Abstract: In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.

公开(公告)号：US10223123B1

公开(公告)日：2019-03-05

申请号：US15133804

申请日：2016-04-20

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F1/3287 ,  G06F1/3234

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

公开(公告)号：US20250103492A1

公开(公告)日：2025-03-27

申请号：US18582305

申请日：2024-02-20

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  Dennis R. Bradford ,  Gaurav Garg ,  Jeff Gonion ,  Bernard J. Semeria ,  James Vash ,  Richard F. Russo

IPC: G06F12/0808 ,  G06F12/0882 ,  G06F12/1045

Abstract: Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

公开(公告)号：US11886340B1

公开(公告)日：2024-01-30

申请号：US17818660

申请日：2022-08-09

Applicant: Apple Inc.

Inventor： Jonathan Y. Tong ,  David E. Kroesche ,  Brett S. Feero

IPC: G06F12/08 ,  G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G06F2212/60

Abstract: A processor configured for real-time transaction processing is disclosed. A processor circuit includes configuration registers that designate a first range of physical memory addresses as reserved for real-time memory requests and a second, non-overlapping range of physical memory addresses that are shared between real-time and non-real-time memory requests. In response to determining that a memory request is associated with an address in the first range, the processor tags the request as a real-time request. The configuration registers may also store information designating portions of one or more cache memories and one or more buffers as being reserved for real-time memory requests. During arbitration, real-time memory requests are given priority over older, non-real-time memory requests.

公开(公告)号：US11755328B2

公开(公告)日：2023-09-12

申请号：US17527872

申请日：2021-11-16

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/3814 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/3816 ,  G06F9/3877 ,  G06F9/4881 ,  G06F9/522

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US11556485B1

公开(公告)日：2023-01-17

申请号：US17462416

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Jonathan Ying Fai Tong ,  Brett S. Feero ,  Christopher L. Colletti ,  David Edward Kroesche ,  Gagan Anand ,  Matthew C. Stone ,  So Min Song

IPC: G06F13/24 ,  G06F12/0879

Abstract: A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

公开(公告)号：US11093249B2

公开(公告)日：2021-08-17

申请号：US16292003

申请日：2019-03-04

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F9/38 ,  G06F9/30 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3206 ,  G06F12/0875

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.