公开(公告)号：US20220334997A1

公开(公告)日：2022-10-20

申请号：US17337805

申请日：2021-06-03

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg

IPC: G06F13/40 ,  G06F15/173

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

公开(公告)号：US12007895B2

公开(公告)日：2024-06-11

申请号：US17821305

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Sergio Kolor ,  Sergio V. Tota ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Jonathan M. Redshaw ,  Steven R. Hutsell ,  Harshavardhan Kaushikkar ,  Shawn M. Fukami

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/109 ,  G06F12/128 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US11972140B2

公开(公告)日：2024-04-30

申请号：US18069033

申请日：2022-12-20

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1045 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20170076417A1

公开(公告)日：2017-03-16

申请号：US14850553

申请日：2015-09-10

Applicant: Apple Inc.

Inventor： Eran Tamari

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G09G5/006 ,  G09G5/363 ,  G09G5/393 ,  G09G2340/02 ,  G09G2360/18 ,  G09G2370/10 ,  G09G2370/12 ,  G09G2370/16

Abstract: Techniques are disclosed relating to rendering display frames. In one embodiment, an integrated circuit is disclosed that includes display pipeline circuitry configured to produce, for a display device, a sequence of frames that includes a first frame and a second, subsequent frame. The display pipeline circuitry is configured to identify pixels of the second frame that differ from pixels of the first frame, and to transmit, to the display device, both the content of identified, differing pixels and a bitmap. In such an embodiment, the bitmap indicates which pixels of the second frame differ from pixels of the first frame. In some embodiments, the display pipeline circuitry includes a comparator circuit configured to generate the bitmap by comparing the pixels of the second frame with the pixels of the first frame.

Abstract translation: 公开了涉及渲染显示帧的技术。 在一个实施例中，公开了一种集成电路，其包括显示管线电路，其被配置为为显示设备产生包括第一帧和第二后续帧的帧序列。 显示管线电路被配置为识别与第一帧的像素不同的第二帧的像素，并且向显示装置发送识别的不同像素的内容和位图。 在这样的实施例中，位图指示第二帧的哪些像素与第一帧的像素不同。 在一些实施例中，显示管线电路包括比较器电路，其被配置为通过将第二帧的像素与第一帧的像素进行比较来生成位图。

公开(公告)号：US20230239252A1

公开(公告)日：2023-07-27

申请号：US17868495

申请日：2022-07-19

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Lior Zimet ,  Opher D. KAHN ,  Eran Tamari ,  Tzach Zemer ,  Per H. Hammarlund

IPC: H04L49/25 ,  H04L47/10

CPC classification number: H04L49/25 ,  H04L47/39

Abstract: In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.

公开(公告)号：US11675722B2

公开(公告)日：2023-06-13

申请号：US17337805

申请日：2021-06-03

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg ,  Lior Zimet ,  Harshavardhan Kaushikkar ,  Steven Fishwick ,  Steven R. Hutsell ,  Shawn M. Fukami

IPC: G06F13/40 ,  G06F15/173

CPC classification number: G06F13/4027 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17381

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

公开(公告)号：US10019968B2

公开(公告)日：2018-07-10

申请号：US15271085

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Yafei Bi ,  Arthur L. Spence ,  Vanessa C. Heppolette ,  Eran Tamari ,  Josh P. DeCesare

IPC: G09G5/12 ,  G09G5/18 ,  G09G5/395 ,  G09G5/39 ,  G09G5/00 ,  G09G5/393

CPC classification number: G09G5/39 ,  G09G5/001 ,  G09G5/12 ,  G09G5/18 ,  G09G5/393 ,  G09G5/395 ,  G09G2310/04 ,  G09G2340/0435 ,  G09G2360/18

Abstract: Systems and methods for synchronizing a video source and display circuitry using a dynamic tearing effect (TE) signal are provided. In one embodiment, an electronic display device includes: variable refresh rate circuitry that, when no new frame data is provided to the electronic display device, extends a vertical blanking period and reduces a refresh rate of the electronic display device. A tearing effect signal is generated, which is selectively set to a first logical level at a first period of time and a second logical level at a second period of time. The tearing effect signal is provided to the host electronic device that provides frame data to the electronic display device and upon receipt of new frame data, an un-extended vertical blanking period is returned to and the frame data at the next frame boundary is displayed.