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公开(公告)号：US20220269619A1
公开(公告)日：2022-08-25
申请号：US17654726
申请日：2022-03-14
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Pratik Chandresh Shah , Tatsuya Iwamoto , David E. Roberts
IPC: G06F12/1027
Abstract: One disclosed embodiment includes a method for memory management. The method includes receiving a first request to clear one or more entries of a translation lookaside buffer (TLB), receiving a second request to clear one or more entries of the TLB, bundling the first request with the second request, determining that a processor associated with the TLB transitioned to an inactive mode, and dropping the bundled first and second requests based on the determination.
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公开(公告)号：US20220261290A1
公开(公告)日：2022-08-18
申请号：US17661624
申请日：2022-05-02
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Michael Imbrogno
Abstract: In general, embodiments are disclosed herein for tracking and allocating graphics hardware resources. In one embodiment, a software and/or firmware process constructs a cross-application command queue utilization table based on one or more specified command queue quality of service (QoS) settings, in order to track the target and current utilization rates of each command queue on the graphics hardware over a given frame and to load work onto the graphics hardware in accordance with the utilization table. Based on the constructed utilization table for a given frame, any command queues that have exceed their respective target utilization value may be moved to an “inactive” status for the duration of the current frame. For any command queues that remain in an “active” status for the current frame, work from those command queues may be loaded on to slots of the appropriate data masters of the graphics hardware in any desired order.
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公开(公告)号：US11321134B2
公开(公告)日：2022-05-03
申请号：US16795814
申请日：2020-02-20
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Michael Imbrogno
Abstract: In general, embodiments are disclosed herein for tracking and allocating graphics hardware resources. In one embodiment, a software and/or firmware process constructs a cross-application command queue utilization table based on one or more specified command queue quality of service (QoS) settings, in order to track the target and current utilization rates of each command queue on the graphics hardware over a given frame and to load work onto the graphics hardware in accordance with the utilization table. Based on the constructed utilization table for a given frame, any command queues that have exceed their respective target utilization value may be moved to an “inactive” status for the duration of the current frame. For any command queues that remain in an “active” status for the current frame, work from those command queues may be loaded on to slots of the appropriate data masters of the graphics hardware in any desired order.
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公开(公告)号：US10719970B2
公开(公告)日：2020-07-21
申请号：US15864833
申请日：2018-01-08
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Rohan Sanjeev Patil , Pratik Chandresh Shah , Gokhan Avkarogullari , Tatsuya Iwamoto
Abstract: One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.
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公开(公告)号：US20190340723A1
公开(公告)日：2019-11-07
申请号：US16511742
申请日：2019-07-15
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Kutty Banerjee , Rohan Sanjeev Patil
Abstract: Systems, methods, and computer readable media to improve task switching operations in a graphics processing unit (GPU) are described. As disclosed herein, the clock rate (and voltages) of a GPU's operating environment may be altered so that a low priority task may be rapidly run to a task switch boundary (or completion) so that a higher priority task may begin execution. In some embodiments, only the GPU's operating clock (and voltage) is increased during the task switch operation. In other embodiments, the clock rate (voltages) of supporting components may also be increased. For example, the operating clock for the GPU's supporting memory, memory controller or memory fabric may also be increased. Once the lower priority task has been swapped out, one or more of the clocks (and voltages) increased during the switch operation could be subsequently decreased, though not necessarily to their pre-switch rates.
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Patent Agency Ranking
公开(公告)号：US20180349146A1
公开(公告)日：2018-12-06
申请号：US15615412
申请日：2017-06-06
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Kutty Banerjee , Benjiman L. Goodman , Terence M. Potter
Abstract: In general, techniques are disclosed for tracking and allocating graphics processor hardware over specified periods of time. More particularly, hardware sensors may be used to determine the utilization of graphics processor hardware after each of a number of specified intervals (referred to as “sample intervals”). The utilization values so captured may be combined after a first number of sample intervals (the combined interval referred to as an “epoch interval”) and used to determine a normalized utilization of the graphic processor's hardware resources. Normalized epoch utilization values have been adjusted to account for resources used by concurrently executing processes. In some embodiments, a lower priority process that obtains and fails to release resources that should be allocated to one or more higher priority processes may be detected, paused, and its hardware resources given to the higher priority processes.
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公开(公告)号：US20160358305A1
公开(公告)日：2016-12-08
申请号：US14851629
申请日：2015-09-11
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Eric O. Sunalp , Tatsuya Iwamoto
IPC: G06T1/20
CPC classification number: G06T1/20 , G06F9/5044 , G06F9/505 , G06F2209/5021 , G06T2200/28
Abstract: Embodiments are directed toward systems and methods for scheduling resources of a graphics processing unit that determine, for a number of applications having commands to be issued to the GPU, a static priority level and a dynamic priority level of each application, work iteratively across static priority levels until a resource budget of the GPU is consumed, and starting with a highest static priority identify the applications in a present static priority level, assign a processing budget of the GPU to each of the applications in the present static priority level according to their dynamic priority levels, and admit to a queue commands from the applications in the present static priority level according to their processing budgets, and release the queue to the GPU.
Abstract translation: 实施例针对用于调度图形处理单元的资源的系统和方法，其针对具有要发布给GPU的命令的多个应用程序确定每个应用的静态优先级和动态优先级，跨静态优先级 直到GPU的资源预算被消耗，并以最高的静态优先级开始以当前静态优先级级别识别应用，根据它们的动态向当前静态优先级中的每一个应用分配GPU的处理预算 优先级，并根据其处理预算承认来自当前静态优先级的应用程序的命令，并将队列释放到GPU。
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公开(公告)号：US20230077058A1
公开(公告)日：2023-03-09
申请号：US17468328
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Benjamin Bowman , Fergus W. MacGarry , Kutty Banerjee , Pratik Chandresh Shah
Abstract: Disclosed techniques relate to distributing graphics work based on priority. In some embodiments, circuitry implements a plurality of tracking slots for sets of graphics work. A set of graphics processor sub-units may each implement multiple distributed hardware slots. Control circuitry may attempt to assign a first set of graphics work having a first priority to a graphics processor sub-unit that is currently executing graphics work having an equal or higher priority than the first priority, where the first set of graphics work is from a first tracking slot. The control circuitry may, in response to a failure of the attempt, generate a signal to graphics software that indicates the failure, wherein the signal indicates the first tracking slot. Disclosed techniques may reduce or avoid problems relating to higher priority work being scheduled behind lower priority work.
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公开(公告)号：US11593175B2
公开(公告)日：2023-02-28
申请号：US17661624
申请日：2022-05-02
Applicant: Apple Inc.
Inventor： Kutty Banerjee , Michael Imbrogno
Abstract: In general, embodiments are disclosed herein for tracking and allocating graphics hardware resources. In one embodiment, a software and/or firmware process constructs a cross-application command queue utilization table based on one or more specified command queue quality of service (QoS) settings, in order to track the target and current utilization rates of each command queue on the graphics hardware over a given frame and to load work onto the graphics hardware in accordance with the utilization table. Based on the constructed utilization table for a given frame, any command queues that have exceed their respective target utilization value may be moved to an “inactive” status for the duration of the current frame. For any command queues that remain in an “active” status for the current frame, work from those command queues may be loaded on to slots of the appropriate data masters of the graphics hardware in any desired order.
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公开(公告)号：US11243598B2
公开(公告)日：2022-02-08
申请号：US16426633
申请日：2019-05-30
Applicant: Apple Inc.
Inventor： Tatsuya Iwamoto , Jason P. Jane , Rohan Sanjeev Patil , Kutty Banerjee , Subodh Asthana , Kyle J. Haughey
IPC: G06F1/32 , G06F1/3234 , G06F1/3287 , G06T1/20 , G06F17/18 , G06F1/3228
Abstract: Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.
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