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    Protection Layer for Halftone Process of Third Metal
    11.
    发明申请
    Protection Layer for Halftone Process of Third Metal 有权
    第三金属半色调工艺保护层

    公开(公告)号：US20140091390A1

    公开(公告)日：2014-04-03

    申请号：US13631385

    申请日：2012-09-28

    Applicant: APPLE INC.

    Inventor： Ming-Chin Hung ,  Byung Duk Yang ,  Kyung Wook Kim ,  Shih Chang Chang

    IPC: H01L29/786 ,  H01L21/768

    CPC classification number: H01L21/768 ,  H01L21/76802 ,  H01L21/76838 ,  H01L27/1248 ,  H01L27/1288

    Abstract: A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive element that may serve as a conductive path between a common electrode and the drain of the transistor.

    Abstract translation: 一种具有用于平坦化层的保护层的薄膜晶体管。 保护层防止灰化过程中平坦化层的减少，从而防止形成通过平坦化层的急剧变细的通孔。 以这种方式，通孔可以涂覆有可以用作公共电极和晶体管的漏极之间的导电路径的导电元件。

    Pixel Architecture for Electronic Displays
    12.
    发明申请
    Pixel Architecture for Electronic Displays 审中-公开
    电子显示器像素架构

    公开(公告)号：US20130335658A1

    公开(公告)日：2013-12-19

    申请号：US13629524

    申请日：2012-09-27

    Applicant: APPLE INC.

    Inventor： Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee ,  Young Bae Park

    IPC: G02F1/136

    CPC classification number: G09G3/3648 ,  G02F1/136227 ,  G02F1/136286 ,  G09G2300/0426

    Abstract: An electronic display for providing a visual or video output for an electronic device. The electronic device includes a transistor layer configured to activate a first pixel row and a second pixel row. For each pixel in the first pixel row and the second pixel row, the transistor layer includes a switch transistor, a pixel electrode, and a common electrode. The electronic device further includes a pixel controller for selectively activating each pixel. The pixel controller includes a first gate line, a first drive line, and a second drive line. During operation, the first gate line provides a charge to the pixel electrode for a first pixel in the first pixel row and for a second pixel in the second pixel row, and the first drive line activates the switch transistor for the first pixel, and the second drive line activates the switch transistor for the second pixel.

    Abstract translation: 一种用于为电子设备提供视觉或视频输出的电子显示器。 电子设备包括被配置为激活第一像素行和第二像素行的晶体管层。 对于第一像素行和第二像素行中的每个像素，晶体管层包括开关晶体管，像素电极和公共电极。 电子设备还包括用于选择性地激活每个像素的像素控制器。 像素控制器包括第一栅极线，第一驱动线和第二驱动线。 在操作期间，第一栅极线为第一像素行中的第一像素和第二像素行中的第二像素向像素电极提供电荷，并且第一驱动线激活用于第一像素的开关晶体管， 第二驱动线激活用于第二像素的开关晶体管。

    Pixel array antialiasing to accommodate curved display edges
    15.
    发明授权
    Pixel array antialiasing to accommodate curved display edges 有权

    公开(公告)号：US10409118B1

    公开(公告)日：2019-09-10

    申请号：US15498356

    申请日：2017-04-26

    Applicant: Apple Inc.

    Inventor： Pei-En Chang ,  Szu-Hsien Lee ,  Hsin-Ying Chiu ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Hossein Nemati

    IPC: G02F1/1343 ,  G02F1/1335 ,  G02F1/1333 ,  H01L27/32 ,  G02F1/133

    Abstract: An electronic device may have a housing and a display in the housing. The display may have one or more curved edges such as curved edges associated with rounded corners in the display and housing. The display may have an array of pixels. The display may include full-strength pixels and may have a band of antialiasing pixels having selectively reduced strengths to visually smooth content displayed along the curved edges. The pixels may be organic light-emitting diode pixels, liquid crystal display pixels, or other display pixels. Organic light-emitting diode pixels may have drive transistors and associated organic light-emitting diodes. Selectively elevated series or opaque light blocking structures of selectively reduced areas may be used to selectively reduce the strength of the antialiasing pixels. Liquid crystal display pixels may include electrodes of different shapes and/or opaque layer openings of different sizes to form antialiasing pixels in desired patterns.

    Display gate driver circuits with dual pulldown transistors
    16.
    发明授权
    Display gate driver circuits with dual pulldown transistors 有权

    公开(公告)号：US10037738B2

    公开(公告)日：2018-07-31

    申请号：US14862071

    申请日：2015-09-22

    Applicant: Apple Inc.

    Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC: G09G3/36 ,  G09G3/3225 ,  G09G3/20

    CPC classification number: G09G3/3674 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291

    Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.

    High refresh rate displays with synchronized local dimming
    17.
    发明授权
    High refresh rate displays with synchronized local dimming 有权

    公开(公告)号：US09984638B2

    公开(公告)日：2018-05-29

    申请号：US14828849

    申请日：2015-08-18

    Applicant: Apple Inc.

    Inventor： Byung Duk Yang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Young-Jik Jo

    IPC: G09G3/36

    CPC classification number: G09G3/3648 ,  G09G3/3611 ,  G09G2300/023 ,  G09G2320/103 ,  G09G2340/0435

    Abstract: A display may have a first stage such as a color liquid crystal display stage and a second stage such as a monochromatic liquid crystal display stage that are coupled in tandem so that light from a backlight passes through both stages. The first (upper) stage may be a high resolution display panel that is operated at a first refresh rate while the second (lower) stage is a low resolution display panel that is operated at a second refresh rate that is greater than the first refresh rate. In particular, the second stage may be configured to provide localized dimming that is synchronized to one or more moving objects in the video frames to be displayed to help reduce the perceived motion blur. The localized dimming may be provided via insertion of a black image portion that only overlaps with the moving objects, a blanking row that tracks the moving objects, a black frame, etc.

    Display Gate Driver Circuits with Dual Pulldown Transistors
    19.
    发明申请
    Display Gate Driver Circuits with Dual Pulldown Transistors 审中-公开
    显示具有双下拉晶体管的栅极驱动器电路

    公开(公告)号：US20170004790A1

    公开(公告)日：2017-01-05

    申请号：US14862071

    申请日：2015-09-22

    Applicant: Apple Inc.

    Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC: G09G3/36 ,  G09G3/32

    CPC classification number: G09G3/3674 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291

    Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.

    Abstract translation: 提供了一种显示器，其包括用于向显示像素提供数据和栅极线信号的显示像素阵列和栅极驱动器电路。 栅极驱动器电路可以包括产生栅极线信号的栅极驱动器电路。 栅极驱动器电路可以包括至少缓冲晶体管，耦合到缓冲晶体管的自举电容器，与缓冲晶体管串联耦合的下拉晶体管，以及耦合到下拉晶体管的栅极的隔离晶体管。 缓冲晶体管可以直接接收第一时钟信号，而隔离晶体管可以直接接收与第一时钟信号互补的第二时钟信号。 下拉晶体管实质上大于缓冲晶体管。 缓冲晶体管基本上大于隔离晶体管。 如此配置，时钟负载最小化，而下拉晶体管的尺寸设置为提供所需的下降时间性能。

    Liquid Crystal Displays With Minimized Transmission Loss and Enhanced Off-Axis Color Fidelity
    20.
    发明申请
    Liquid Crystal Displays With Minimized Transmission Loss and Enhanced Off-Axis Color Fidelity 有权
    具有最小化传输损耗和增强的离轴色彩保真度的液晶显示器

    公开(公告)号：US20160209691A1

    公开(公告)日：2016-07-21

    申请号：US14850006

    申请日：2015-09-10

    Applicant: Apple Inc.

    Inventor： Byung Duk Yang ,  Chia Hsuan Tai ,  Hiroshi Osawa ,  Kyung Wook Kim ,  Ming-Chin Hung ,  Shang-Chih Lin ,  Shih Chang Chang ,  Yu Cheng Chen ,  Yuan Chen

    IPC: G02F1/1368 ,  H01L29/51 ,  H01L29/786 ,  G02F1/1335 ,  G02F1/1362

    CPC classification number: G02F1/1368 ,  G02B6/00 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/133514 ,  G02F1/133528 ,  G02F1/1362 ,  G02F1/136209 ,  G02F2001/133521 ,  G02F2001/136222 ,  H01L29/518 ,  H01L29/78606

    Abstract: A display may have upper and lower display layers. A layer of liquid crystal material may be interposed between the upper and lower display layers. The display layers may have substrates. The display layers may include a color filter layer having an array of color filter elements on a glass substrate and a thin-film transistor layer having a layer of thin-film transistor circuitry on a glass substrate. Dielectric layers within the display layers such as dielectric layers within the thin-film transistor layer may have differing indices of refraction. Reflections and color shifts due to index of refraction discontinuities may be minimized by interposing graded index dielectric layers between adjacent layers with different indices. The graded index layers may be formed from structures with a continuously varying index of refraction or structures with a step-wise varying index of refraction.

    Abstract translation: 显示器可以具有上和下显示层。 可以在上显示层和下显示层之间插入一层液晶材料。 显示层可以具有基底。 显示层可以包括在玻璃基板上具有滤色器元件阵列的滤色器层和在玻璃基板上具有薄膜晶体管电路层的薄膜晶体管层。 诸如薄膜晶体管层内的介电层的显示层内的电介质层可以具有不同的折射率。 由于折射不连续指数引起的反射和颜色偏移可以通过在不同指数的相邻层之间插入渐变折射率介电层来最小化。 渐变折射率层可以由具有连续变化的折射率的结构或具有逐步变化的折射率的结构形成。

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