公开(公告)号：US09104329B2

公开(公告)日：2015-08-11

申请号：US14305488

申请日：2014-06-16

Applicant: Apple Inc.

Inventor： Daniel J. Post ,  Nir Jacob Wakrat ,  Vadim Khmelnitsky

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/14 ,  G06F17/30 ,  G06F12/02

CPC classification number: G06F3/0643 ,  G06F11/1417 ,  G06F11/1435 ,  G06F12/0246 ,  G06F17/30218

Abstract: Systems and methods are disclosed for mount-time reconciliation of data availability. During system boot-up, a non-volatile memory (“NVM”) driver can be enumerated, and an NVM driver mapping can be obtained. The NVM driver mapping can include the actual availability of LBAs in the NVM. A file system can then be mounted, and a file system allocation state can be generated. The file system allocation state can indicate the file system's view of the availability of LBAs. Subsequently, data availability reconciliation can be performed. That is, the file system allocation state and the NVM driver mapping can be overlaid and compared with one another in order to expose any discrepancies.

Abstract translation: 披露了数据可用性的安装时间调节的系统和方法。 在系统启动期间，可以列举非易失性存储器（“NVM”）驱动程序，并且可以获得NVM驱动程序映射。 NVM驱动程序映射可以包括NVM中LBA的实际可用性。 然后可以安装文件系统，并且可以生成文件系统分配状态。 文件系统分配状态可以指示文件系统对LBA可用性的视图。 随后，可以执行数据可用性协调。 也就是说，文件系统分配状态和NVM驱动程序映射可以被叠加并相互比较，以便暴露任何差异。

公开(公告)号：US08862851B2

公开(公告)日：2014-10-14

申请号：US13725671

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Tahoma Toelkes ,  Nir Jacob Wakrat ,  Kenneth L Herman ,  Barry Corlett ,  Vadim Khmelnitsky ,  Anthony Fai ,  Daniel Jeffrey Post ,  Hsiao Thio

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/7208

Abstract: The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Abstract translation: 所公开的架构使用地址映射将主机接口上的块地址映射到非易失性存储器（NVM）设备的内部块地址。 块地址映射到用于选择由块地址标识的可并行寻址单元（CAU）的内部芯片选择。 所公开的架构支持用于读取，写入，擦除和获取状态操作的通用NVM命令。 该架构还支持扩展命令集，以支持利用多个CAU架构的读写操作。

公开(公告)号：US20130073800A1

公开(公告)日：2013-03-21

申请号：US13676729

申请日：2012-11-14

Applicant: APPLE INC.

Inventor： Vadim Khmelnitsky ,  Nir Jacob Wakrat ,  Tahoma Toelkes ,  Daniel Jeffrey Post ,  Anthony Fai

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Abstract translation: 公开了用于非易失性存储器系统的多位准备命令。 多功能准备命令提供可用于准备非易失性存储器设备的数据，用于即将进行的多页程序操作。 主机控制器可以使用多页面程序操作之前的命令来优化多页面程序命令的使用。 非易失性存储器件可以使用这些命令来配置非易失性存储器以准备随后的操作，例如改变命令顺序或使用用于后续操作的最优化的命令集。

公开(公告)号：US09189386B2

公开(公告)日：2015-11-17

申请号：US13830233

申请日：2013-03-14

Applicant: Apple Inc.

Inventor： Nir Jacob Wakrat ,  Tahoma M. Toelkes

IPC: G06F12/02 ,  G11C11/56

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5641

Abstract: Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.

Abstract translation: 提供了系统和方法，用于将每个单元的位数动态地分配给非易失性存储器（“NVM”）设备的存储单元。 在一些实施例中，主机可以使用SLC编程或MLC编程操作来确定是否在NVM设备中存储数据。 基于该确定，主机可以将擦除的块分配为SLC块或MLC块，而不管擦除的块是否先前用作SLC块，MLC块或两者。 在一些实施例中，为了动态地将存储器位置分配为SLC或MLC，主机可以向NVM包提供地址向量，其中地址向量可以指定用于该存储器位置的存储器位置和每个单元的位数。

公开(公告)号：US09164680B2

公开(公告)日：2015-10-20

申请号：US14147700

申请日：2014-01-06

Applicant: Apple Inc.

Inventor： Nicholas C. Seroff ,  Anthony Fai ,  Nir Jacob Wakrat

IPC: G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0635 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/1684 ,  G06F2212/7204 ,  Y02D10/154

Abstract: Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.

Abstract translation: 提供了用于在非易失性存储器（“NVM”）系统中改善通信的系统和方法。 系统可以在多个通信通道之间切换，以提供主机设备与系统中包含的NVM管芯之间的点对点通信。 主机设备可以在扩展到系统的一个或多个存储器控制器的多个通信通道之间切换，并且存储器控制器可以在延伸到NVM管芯的多个通信通道之间切换。 功率岛可以并入到系统中以电隔离与非活动通信信道相关联的系统组件。

公开(公告)号：US20140136771A1

公开(公告)日：2014-05-15

申请号：US14160763

申请日：2014-01-22

Applicant: Apple Inc.

Inventor： Michael J. Cornwell ,  Christopher P. Dudte ,  Nir Jacob Wakrat

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F2212/1016 ,  G06F2212/7211

Abstract: Systems and processes may use a host and an external host. The host may be a portable device that includes a memory, a memory controller, and a communication interface for communication with the external host. The portable device may receive a command signal from the external host and initiate a predetermined amount of wear leveling in response to the command signal.

Abstract translation: 系统和进程可以使用主机和外部主机。 主机可以是包括存储器，存储器控制器和用于与外部主机通信的通信接口的便携式设备。 便携式设备可以从外部主机接收命令信号，并响应于命令信号启动预定量的磨损均衡。

公开(公告)号：US20140019673A1

公开(公告)日：2014-01-16

申请号：US13830233

申请日：2013-03-14

Applicant: Apple Inc.

Inventor： Nir Jacob Wakrat ,  Tahoma M. Toelkes

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5641

Abstract: Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.

Abstract translation: 提供了系统和方法，用于将每个单元的位数动态地分配给非易失性存储器（“NVM”）设备的存储单元。 在一些实施例中，主机可以使用SLC编程或MLC编程操作来确定是否在NVM设备中存储数据。 基于该确定，主机可以将擦除的块分配为SLC块或MLC块，而不管擦除的块是否先前用作SLC块，MLC块或两者。 在一些实施例中，为了动态地将存储器位置分配为SLC或MLC，主机可以向NVM包提供地址向量，其中地址向量可以指定用于该存储器位置的存储器位置和每个单元的位数。

公开(公告)号：US08612791B2

公开(公告)日：2013-12-17

申请号：US13918240

申请日：2013-06-14

Applicant: Apple Inc.

Inventor： Nir Jacob Wakrat ,  Anthony Fai ,  Matthew Byom

IPC: G06F1/00

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

Abstract translation: 在非易失性存储器系统中，物理上分离的电源轨从主机系统提供给NVM设备，用于独立地对NVM设备中的控制器和存储器阵列进行电力循环。 NVM设备的控制器可以通过主机通道向主机系统发送电源循环请求信号，或更新NVM设备中的状态寄存器。 主机系统接收并解码电源周期请求信号，或读取状态寄存器，并执行电源循环请求，其中可以包括对NVM设备中的控制器或存储器阵列进行电源循环，或两者兼而有之。 功率循环请求可以基于非易失性存储器系统的功率状态，其可以由控制器或主机系统管理，或两者兼而有之。

公开(公告)号：US20130212318A1

公开(公告)日：2013-08-15

申请号：US13725671

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Tahoma Toelkes ,  Nir Jacob Wakrat ,  Kenneth L. Herman ,  Barry Corlett ,  Vadim Khmelnitsky ,  Anthony Fai ,  Daniel Jeffrey Post ,  Hsiao Thio

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/7208

Abstract: The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Abstract translation: 所公开的架构使用地址映射将主机接口上的块地址映射到非易失性存储器（NVM）设备的内部块地址。 块地址映射到用于选择由块地址标识的可并行寻址单元（CAU）的内部芯片选择。 所公开的架构支持用于读取，写入，擦除和获取状态操作的通用NVM命令。 该架构还支持扩展命令集，以支持利用多个CAU架构的读写操作。

公开(公告)号：US20130132653A1

公开(公告)日：2013-05-23

申请号：US13740620

申请日：2013-01-14

Applicant: APPLE INC.

Inventor： Daniel J. Post ,  Matthew J. Byom ,  Vadim Khmelnitsky ,  Nir Jacob Wakrat ,  Kenneth Herman

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0643 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C29/52

Abstract: Systems and methods are disclosed for partitioning data for storage in a non-volatile memory (“NVM”), such as flash memory. In some embodiments, a priority may be assigned to data being stored, and the data may be logically partitioned based on the priority. For example, a file system may identify a logical address within a first predetermined range for higher priority data and within a second predetermined range for lower priority data, such using a union file system. Using the logical address, a NVM driver can determine the priority of data being stored and can process (e.g., encode) the data based on the priority. The NVM driver can store an identifier in the NVM along with the data, and the identifier can indicate the processing techniques used on the associated data.

Abstract translation: 公开了用于分割用于存储在诸如闪存的非易失性存储器（“NVM”）中的数据的系统和方法。 在一些实施例中，可以将优先级分配给正在存储的数据，并且可以基于优先级逻辑地划分数据。 例如，文件系统可以识别用于较高优先级数据的第一预定范围内的逻辑地址，并且在较低优先权数据的第二预定范围内识别逻辑地址，诸如使用联合文件系统。 使用逻辑地址，NVM驱动器可以确定正在存储的数据的优先级，并且可以基于优先级处理（例如，编码）数据。 NVM驱动程序可以将数据与NVM一起存储在标识符中，并且标识符可以指示在相关数据上使用的处理技术。