公开(公告)号：US10515028B2

公开(公告)日：2019-12-24

申请号：US16030794

申请日：2018-07-09

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Brijesh Tripathi ,  Kiran Kattel ,  Rakesh L. Notani ,  Fabien S. Faure ,  Sukalpa Biswas ,  Kai Lun Hsiung ,  Neeraj Parik ,  Venkata Ramana Malladi ,  Shiva Kumar ,  Chaitanya Polapragada ,  Allen Kim

IPC: G06F13/16

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

公开(公告)号：US20190187189A1

公开(公告)日：2019-06-20

申请号：US15848804

申请日：2017-12-20

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Fabien S. Faure ,  Rakesh L. Notani

IPC: G01R19/165 ,  G11C5/14 ,  G11C5/02 ,  G11C7/10 ,  G11C8/12

CPC classification number: G01R19/16566 ,  G06F13/1668 ,  G11C5/02 ,  G11C5/147 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4093 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2207/2254

Abstract: A method and apparatus for predicting a reference voltage in a memory subsystem is disclosed. A memory subsystem includes a memory controller coupled to a memory. The memory controller includes a lookup table having a number of different reference voltage values each corresponding to one of a number of different performance states. The memory controller further includes calibration circuitry configured to determine reference voltages for operation in various performance states. Responsive to returning to a performance state after operating in another, the calibration circuitry may restore the reference voltage to its most recently used value, and also obtain a predicted reference voltage. Calibrations may be performed at both the restored reference voltage and the predicted reference voltage obtained from the lookup table. The subsequent operating reference voltage may then be selected based on which of the two calibrations resulted in the largest data eye width.

公开(公告)号：US20190042492A1

公开(公告)日：2019-02-07

申请号：US16030794

申请日：2018-07-09

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Brijesh Tripathi ,  Kiran Kattel ,  Rakesh L. Notani ,  Fabien S. Faure ,  Sukalpa Biswas ,  Kai Lun Hsiung ,  Neeraj Parik ,  Venkata Ramana Malladi ,  Shiva Kumar ,  Chaitanya Polapragada ,  Allen Kim

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1689 ,  Y02D10/14

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

公开(公告)号：US10019387B2

公开(公告)日：2018-07-10

申请号：US14676174

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Brijesh Tripathi ,  Kiran Kattel ,  Rakesh L. Notani ,  Fabien S. Faure ,  Sukalpa Biswas ,  Kai Lun Hsiung ,  Neeraj Parik ,  Venkata Ramana Malladi ,  Shiva Kumar ,  Chaitanya Polapragada ,  Allen Kim

IPC: G06F13/00 ,  G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1689 ,  Y02D10/14

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

公开(公告)号：US20160292094A1

公开(公告)日：2016-10-06

申请号：US14676174

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Brijesh Tripathi ,  Kiran Kattel ,  Rakesh L. Notani ,  Fabien S. Faure ,  Sukalpa Biswas ,  Kai Lun Hsiung ,  Neeraj Parik ,  Venkata Ramana Malladi ,  Shiva Kumar ,  Chaitanya Polapragada ,  Allen Kim

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1689 ,  Y02D10/14

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许在通信链路上执行周期性校准操作。 控制器可以基于初始值来确定与通信链路一起使用的参考电压的多个可能值。 可以使用每个可能的值执行校准操作，并且基于在校准操作期间测量的数据眼睛的宽度来评估操作的结果。 然后，控制器可以根据多个可能值中的每一个的分数从多个可能值中选择参考电压的新值。

公开(公告)号：US20240094917A1

公开(公告)日：2024-03-21

申请号：US18469730

申请日：2023-09-19

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Rakesh L. Notani

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/023

Abstract: A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

公开(公告)号：US20220270664A1

公开(公告)日：2022-08-25

申请号：US17181979

申请日：2021-02-22

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Venkata Ramana Malladi ,  John H. Kelm ,  Taehyun Kim

IPC: G11C11/4074 ,  G11C11/4096 ,  G11C11/4076 ,  G06F3/06

Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.

公开(公告)号：US11217285B1

公开(公告)日：2022-01-04

申请号：US16986116

申请日：2020-08-05

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan ,  Naveen Kumar Korada

IPC: G11C7/22 ,  G11C7/10 ,  G06F11/10

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

公开(公告)号：US20210183414A1

公开(公告)日：2021-06-17

申请号：US16716616

申请日：2019-12-17

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Alma L. Juarez Dominguez

IPC: G11C5/14 ,  G06F11/07 ,  G06F3/06

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

公开(公告)号：US20200159463A1

公开(公告)日：2020-05-21

申请号：US16751975

申请日：2020-01-24

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.