公开(公告)号：US20180217659A1

公开(公告)日：2018-08-02

申请号：US15935274

申请日：2018-03-26

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III ,  James N. Hardage, JR. ,  Richard F. Russo

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3293 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/5044 ,  G06F9/5094 ,  G06F2009/45579 ,  Y02D10/122 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

公开(公告)号：US09928115B2

公开(公告)日：2018-03-27

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, Jr. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F12/084 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0813

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

公开(公告)号：US09501284B2

公开(公告)日：2016-11-22

申请号：US14502901

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Pradeep Kanapathipillai ,  Richard F. Russo ,  Sandeep Gupta ,  Conrado Blasco

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

Abstract: A processor includes a mechanism that checks for and flushes only speculative loads and any respective dependent instructions that are younger than an executed wait for event (WEV) instruction, and which also match an address of a store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor. The mechanism may allow speculative loads that do not match the address of any store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor.

Abstract translation: 处理器包括一种机制，其仅检查和刷新推测负载以及比执行的等待事件（WEV）指令更年轻的任何相应的依赖指令，并且还匹配已经被确定已被执行的存储指令的地址 在由不同处理器执行配对SEV指令之前由不同的处理器。 该机制可以允许在由不同的处理器执行配对的SEV指令之前，已经确定已被不同处理器执行的任何存储指令的地址不匹配的推测性负载。

公开(公告)号：US20160092236A1

公开(公告)日：2016-03-31

申请号：US14502901

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Pradeep Kanapathipaillai ,  Richard F. Russo ,  Sandeep Gupta ,  Conrado Blasco

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

Abstract: A processor includes a mechanism that checks for and flushes only speculative loads and any respective dependent instructions that are younger than an executed wait for event (WEV) instruction, and which also match an address of a store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor. The mechanism may allow speculative loads that do not match the address of any store instruction that has been determined to have been executed by a different processor prior to execution of the paired SEV instruction by the different processor.

Abstract translation: 处理器包括一种机制，其仅检查和刷新推测负载以及比执行的等待事件（WEV）指令更年轻的任何相应的依赖指令，并且还匹配已经被确定已被执行的存储指令的地址 在由不同处理器执行配对SEV指令之前由不同的处理器。 该机制可以允许在由不同的处理器执行配对的SEV指令之前，已经确定已被不同处理器执行的任何存储指令的地址不匹配的推测性负载。

公开(公告)号：US12175248B2

公开(公告)日：2024-12-24

申请号：US18305151

申请日：2023-04-21

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Deepankar Duggal ,  Debasish Chandra ,  Niket K Choudhary ,  Richard F. Russo

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a control transfer instruction is mispredicted, a load instruction may have been executed on the wrong path. In disclosed embodiments, result storage circuitry records information that indicates destination registers of speculatively-executed load instructions including a first load instruction. Control flow tracker circuitry may store information indicating a reconvergence point for the control transfer instruction. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine that the first load instruction does not depend on data from any instruction between the control transfer instruction and the reconvergence point, and use, as a result of the first load instruction, a value from a recorded destination register that was written based on speculative execution of the first load, notwithstanding the misprediction of the control transfer instruction.

公开(公告)号：US20240354111A1

公开(公告)日：2024-10-24

申请号：US18305173

申请日：2023-04-21

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Deepankar Duggal ,  Debasish Chandra ,  Niket K. Choudhary ,  Richard F. Russo

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/3005 ,  G06F9/3016

Abstract: Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a first control transfer instruction is mispredicted, a second control transfer instruction may have been executed on the wrong path because of the misprediction. Result storage circuitry may record information indicating a determined direction for the second control transfer instruction. Control flow tracker circuitry may store, for the first control transfer instruction, information indicating a reconvergence point. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine, based on the tracked registers, that the second control transfer instruction does not depend on data from any instruction between the first control transfer instruction and the reconvergence point, and use the recorded determined direction for the second control transfer instruction, notwithstanding the misprediction of the first control transfer instruction.

公开(公告)号：US20210064376A1

公开(公告)日：2021-03-04

申请号：US16551208

申请日：2019-08-26

Applicant: Apple Inc.

Inventor： Deepankar Duggal ,  Conrado Blasco ,  Muawya M. Al-Otoom ,  Richard F. Russo

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for implementing a physical register last reference scheme are described. A system includes a processor with a mapper, history file, and freelist. When an entry in the mapper is updated with a new architectural register-to-physical register mapping, the processor creates a new history file entry for the given instruction that caused the update. The processor also searches the mapper to determine if the old physical register that was previously stored in the mapper entry is referenced by any other mapper entries. If there are no other mapper entries that reference this old physical register, then a last reference indicator is stored in the new history file entry. When the given instruction retires, the processor checks the last reference indicator in the history file entry to determine whether the old physical register can be returned to the freelist of available physical registers.

公开(公告)号：US20180307297A1

公开(公告)日：2018-10-25

申请号：US15496290

申请日：2017-04-25

Applicant: Apple Inc.

Inventor： Bernard Joseph Semeria ,  John H. Mylius ,  Pradeep Kanapathipillai ,  Richard F. Russo ,  Shih-Chieh Wen ,  Richard H. Larson

IPC: G06F1/32 ,  G06F9/38 ,  G06F3/06

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3296 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/067 ,  G06F9/3802

Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.

公开(公告)号：US20170068575A1

公开(公告)日：2017-03-09

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, JR. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。 处理器可以支持多种处理器状态（PState）。 每个PState可以指定工作点（例如，电源电压幅度和时钟频率的组合），并且每个PState可以映射到处理器核心之一。 在运行期间，其中一个核心是活动的：当前PState映射到的核心。 如果选择新的PState并将其映射到不同的核心，则处理器可以自动地将处理器状态切换到新选择的核心，并且可以在该核心上开始执行。 可以使用专用寄存器（SPR）互连来执行上下文切换。 给定处理器中的每个处理器核心可以耦合到SPR互连以允许访问外部SPR。

公开(公告)号：US20250103492A1

公开(公告)日：2025-03-27

申请号：US18582305

申请日：2024-02-20

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  Dennis R. Bradford ,  Gaurav Garg ,  Jeff Gonion ,  Bernard J. Semeria ,  James Vash ,  Richard F. Russo

IPC: G06F12/0808 ,  G06F12/0882 ,  G06F12/1045

Abstract: Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.