公开(公告)号：US20240403532A1

公开(公告)日：2024-12-05

申请号：US18799297

申请日：2024-08-09

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Dany Davidov

IPC: G06F30/392 ,  G06F13/40 ,  G06F115/02

Abstract: A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

公开(公告)号：US20230350828A1

公开(公告)日：2023-11-02

申请号：US18309192

申请日：2023-04-28

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg ,  Lior Zimet ,  Harshavardhan Kaushikkar ,  Steven Fishwick ,  Steven R. Hutsell ,  Shawn M. Fukami

IPC: G06F15/173 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17381

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

公开(公告)号：US11803471B2

公开(公告)日：2023-10-31

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US20230053530A1

公开(公告)日：2023-02-23

申请号：US17821305

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Sergio Kolor ,  Sergio V. Tota ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Jonathan M. Redshaw ,  Steven R. Hutsell ,  Harshavardhan Kaushikkar ,  Shawn M. Fukami

IPC: G06F15/173 ,  G06F15/78 ,  G06F13/16 ,  G06F13/40

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US12277074B1

公开(公告)日：2025-04-15

申请号：US18473614

申请日：2023-09-25

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sandeep Gupta ,  James Vash

IPC: G06F13/14 ,  G06F13/16

Abstract: Techniques are disclosed pertaining to utilizing a communication fabric via multiple ports. An agent circuit includes a plurality of command-and-data ports that couple the agent circuit to a communication fabric coupled to a plurality of hardware components that includes a plurality of memory controller circuits that facilitate access to a memory. The agent circuit can execute an instruction that involves issuing a command for data stored at the memory. The agent circuit may perform a hash operation on a memory address associated with the command to determine which one of the plurality of memory controller circuits to which to issue the command. The agent circuit issues the command to the determined memory controller circuit on a particular one of the plurality of command-and-data ports that is designated to the memory controller circuit. The agent circuit may issue all commands destined to that memory controller circuit on that port.

公开(公告)号：US20250097167A1

公开(公告)日：2025-03-20

申请号：US18404837

申请日：2024-01-04

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Lital Levy-Rubin ,  Lior Zimet ,  Sergio Kolor

IPC: H04L49/253 ,  H04L49/90

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to first and second networks of the computer system. The NSM gateway circuit may route, for example, a message for a non-DRAM transaction from a source agent circuit coupled to the first network but not the second network to a destination agent circuit coupled to the second network but not the first network, and vice-versa. The NSM gateway circuit can also route messages for non-DRAM transactions between source and destination agent circuits both located on the same network. Still further, the NSM gateway circuit can route broadcast (i.e., one-to-many) transactions as well as network element configuration requests. In some implementations, a computer system may have multiple NSM gateway circuits, each assigned to handle non-DRAM transactions from an assigned set of agent circuits.

公开(公告)号：US20240370371A1

公开(公告)日：2024-11-07

申请号：US18607128

申请日：2024-03-15

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  James Vash ,  Gaurav Garg ,  Sergio Kolor ,  Harshavardhan Kaushikkar ,  Ramesh B. Gunna ,  Steven R. Hutsell

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US12112113B2

公开(公告)日：2024-10-08

申请号：US17194003

申请日：2021-03-05

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Dany Davidov ,  Nir Leshem ,  Mark Pilip ,  Lior Zimet

IPC: G06F30/392 ,  G06F13/40 ,  G06F115/02

CPC classification number: G06F30/392 ,  G06F13/4068 ,  G06F2115/02

Abstract: A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

公开(公告)号：US20230388241A1

公开(公告)日：2023-11-30

申请号：US18326246

申请日：2023-05-31

Applicant: Apple Inc.

Inventor： Dany Davidov ,  Nir Leshem ,  Mark Pilip ,  Sergio Kolor

IPC: H04L47/35 ,  H04L69/22 ,  H04L47/32

CPC classification number: H04L47/35 ,  H04L69/22 ,  H04L47/32

Abstract: An apparatus includes an interface circuit and an encoder circuit. The interface circuit is configured to send a data packet via a plurality of segments, and to send an idle value via the plurality of segments when no data packet is available. The idle value is configured to cause a segment in a receiving apparatus to idle. The encoder circuit is configured to receive a particular data packet, and, if a portion of the particular data packet has a same value as the idle value for a subset of the plurality of segments, to replace at least a portion of the data packet with a mask value to generate a modified data packet. The mask value indicates how to recreate the particular data packet. The encoder circuit is further configured to send the modified data packet to the receiving apparatus via the plurality of segments of the interface circuit.

公开(公告)号：US20230239252A1

公开(公告)日：2023-07-27

申请号：US17868495

申请日：2022-07-19

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Lior Zimet ,  Opher D. KAHN ,  Eran Tamari ,  Tzach Zemer ,  Per H. Hammarlund

IPC: H04L49/25 ,  H04L47/10

CPC classification number: H04L49/25 ,  H04L47/39

Abstract: In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.