公开(公告)号：US20220375787A1

公开(公告)日：2022-11-24

申请号：US17323381

申请日：2021-05-18

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Kurtis LESCHKIES ,  Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Tapash CHAKRABORTY ,  Han-Wen CHEN ,  Steven VERHAVERBEKE

IPC: H01L21/768 ,  H01L21/48

Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.

公开(公告)号：US20220171281A1

公开(公告)日：2022-06-02

申请号：US17673951

申请日：2022-02-17

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Han-Wen CHEN ,  Chintan BUCH ,  Steven VERHAVERBEKE ,  Vincent DICAPRIO

IPC: G03F7/00 ,  H01L21/768 ,  G03F7/20

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.

公开(公告)号：US20220139884A1

公开(公告)日：2022-05-05

申请号：US17578271

申请日：2022-01-18

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/522 ,  H01L23/495 ,  H01L25/00

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

公开(公告)号：US20210159160A1

公开(公告)日：2021-05-27

申请号：US16886704

申请日：2020-05-28

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO ,  Bernhard STONAS ,  Jean DELMAS

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20200159113A1

公开(公告)日：2020-05-21

申请号：US16192546

申请日：2018-11-15

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Han-Wen CHEN ,  Chintan BUCH ,  Steven VERHAVERBEKE ,  Vincent DICAPRIO

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/768

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.

公开(公告)号：US20240021533A1

公开(公告)日：2024-01-18

申请号：US18362433

申请日：2023-07-31

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Guan Huei SEE ,  Giback PARK ,  Giorgio CELLERE ,  Diego TONINI ,  Vincent DICAPRIO ,  Kyuil CHO

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/10 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H05K1/02 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/105 ,  H01L23/66 ,  H01Q1/2283 ,  H01Q1/243 ,  H05K1/0243 ,  H01L21/50 ,  H01L21/76802 ,  H01L23/5385 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2021/60007

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

公开(公告)号：US20220028709A1

公开(公告)日：2022-01-27

申请号：US16938517

申请日：2020-07-24

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI ,  Steven VERHAVERBEKE ,  Jean DELMAS ,  Han-Wen CHEN ,  Giback PARK

IPC: H01L21/67 ,  H01L21/48 ,  B23K26/382 ,  B23K26/0622

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.

公开(公告)号：US20210257307A1

公开(公告)日：2021-08-19

申请号：US17227983

申请日：2021-04-12

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Guan Huei SEE ,  Giback PARK ,  Giorgio CELLERE ,  Diego TONINI ,  Vincent DICAPRIO ,  Kyuil CHO

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/10 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H05K1/02 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065 ,  H01L27/06

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

公开(公告)号：US20210257306A1

公开(公告)日：2021-08-19

申请号：US17227811

申请日：2021-04-12

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Giorgio CELLERE ,  Diego TONINI ,  Vincent DICAPRIO ,  Kyuil CHO

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/10 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/24 ,  H05K1/02 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065 ,  H01L27/06

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

公开(公告)号：US20210257289A1

公开(公告)日：2021-08-19

申请号：US17227837

申请日：2021-04-12

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO ,  Bernhard STONAS ,  Jean DELMAS

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.