公开(公告)号：US20170040158A1

公开(公告)日：2017-02-09

申请号：US15230197

申请日：2016-08-05

Applicant: Applied Materials, Inc. ,  The Regents of the University of California

Inventor： Jessica S. KACHIAN ,  Naomi YOSHIDA ,  Mei CHANG ,  Andrew C. KUMMEL ,  Mary EDMONDS

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/0217 ,  H01L21/02211

Abstract: The present disclosure provides for semiconductor fabrication processes that include atomic layer depositions. Embodiments described herein provide for formation of a diffusion barrier or gate dielectric layer in preparation for subsequent ALD on semiconductor surfaces. More specifically, embodiments of the present disclosure provide for the formation of fin field effect transistor (FinFET) and metal oxide semiconductor field effect transistor (MOSFET) devices utilizing improved ALD processes.

Abstract translation: 本公开提供了包括原子层沉积的半导体制造工艺。 本文描述的实施例提供了扩散阻挡层或栅极介电层的形成，以准备半导体表面上的随后的ALD。 更具体地，本公开的实施例提供了利用改进的ALD工艺形成鳍式场效应晶体管（FinFET）和金属氧化物半导体场效应晶体管（MOSFET）器件。

公开(公告)号：US20250006474A1

公开(公告)日：2025-01-02

申请号：US18216432

申请日：2023-06-29

Applicant: Applied Materials, Inc.

Inventor： Naomi YOSHIDA ,  Nobuyuki SASAKI ,  Yoichi SUZUKI ,  Tomoyuki TADA ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01J37/32 ,  C23C16/02 ,  C23C16/24 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  H01L21/768

Abstract: A cluster tool for forming an interconnection structure includes a pre-clean chamber, a selective chemical vapor deposition (CVD) chamber, a plasma-enhanced CVD (PECVD) chamber, one or more transfer chambers coupled to the pre-clean chamber, the selective CVD chamber, and the PECVD chamber, and configured to transfer the interconnection structure between the pre-clean chamber, the selective CVD chamber, and the PECVD chamber without breaking vacuum environment, and a controller configured to cause pre-cleaning of an exposed surface of a metal layer formed within a first dielectric layer of the interconnection structure in the pre-clean chamber, selective deposition of a cap layer on the pre-cleaned surface of the metal layer in the selective CVD chamber, and deposition of deposit a second dielectric layer on the cap layer and an exposed surface of the first dielectric layer in the PECVD chamber.

公开(公告)号：US20240379420A1

公开(公告)日：2024-11-14

申请号：US18781633

申请日：2024-07-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Shi YOU ,  He REN ,  Naomi YOSHIDA ,  Nikolaos BEKIARIS ,  Mehul NAIK ,  Martin Jay SEAMONS ,  Jingmei LIANG ,  Mei-Yee SHEK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/67

Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material

公开(公告)号：US20170309479A1

公开(公告)日：2017-10-26

申请号：US15496982

申请日：2017-04-25

Applicant: Applied Materials, Inc. ,  The Regents of the University of California

Inventor： Naomi YOSHIDA ,  Lin DONG ,  Andrew KUMMEL ,  Jessica KACHIAN ,  Mary EDMONDS ,  Steve WOLF

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02052 ,  H01L21/02112 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/28194

Abstract: Embodiments described herein relate to semiconductor and metal substrate surface preparation and controlled growth methods. An example application is formation of an atomic layer deposition (ALD) control layer as a diffusion barrier or gate dielectric layer and subsequent ALD processing. Embodiments described herein are believed to be advantageously utilized concerning gate oxide deposition, diffusion barrier deposition, surface functionalization, surface passivation, and oxide nucleation, among other processes. More specifically, embodiments described herein provide for silicon nitride ALD processes which functionalize, passivate, and nucleate a SiNx monolayer at temperatures below about 300° C.

公开(公告)号：US20170179252A1

公开(公告)日：2017-06-22

申请号：US15043883

申请日：2016-02-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei V. TANG ,  Paul F. MA ,  Steven C. H. HUNG ,  Michael CHUDZIK ,  Siddarth KRISHNAN ,  Wenyu ZHANG ,  Seshadri GANGULI ,  Naomi YOSHIDA ,  Lin DONG ,  Yixiong YANG ,  Liqi WU ,  Shih Chung CHEN

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66446 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78681

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.

公开(公告)号：US20170018624A1

公开(公告)日：2017-01-19

申请号：US15279257

申请日：2016-09-28

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Benjamin COLOMBEAU ,  Michael CHUDZIK

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/42392 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/15 ,  H01L29/157 ,  H01L29/158 ,  H01L29/66742 ,  H01L29/78696

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离的方法和装置。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 不同的材料可以是含硅材料和一种或多种III / V材料。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。