公开(公告)号：US20180061978A1

公开(公告)日：2018-03-01

申请号：US15804691

申请日：2017-11-06

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi Sun WOOD ,  Nam Sung KIM

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20170194430A1

公开(公告)日：2017-07-06

申请号：US15395928

申请日：2016-12-30

Applicant: Applied Materials, Inc.

Inventor： Bingxi Sun WOOD ,  Michael G. WARD ,  Shiyu SUN ,  Michael CHUDZIK ,  Nam Sung KIM ,  Hua CHUNG ,  Yi-Chiau HUANG ,  Chentsau YING ,  Ying ZHANG ,  Chi-Nung NI ,  Lin DONG ,  Dongqing YANG

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/764 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.

公开(公告)号：US20160336405A1

公开(公告)日：2016-11-17

申请号：US15152273

申请日：2016-05-11

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi WOOD ,  Nam Sung KIM

IPC: H01L29/15 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/45 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离和鳍场效应晶体管（FinFET）隔离的方法和器件结构。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。

公开(公告)号：US20170179252A1

公开(公告)日：2017-06-22

申请号：US15043883

申请日：2016-02-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei V. TANG ,  Paul F. MA ,  Steven C. H. HUNG ,  Michael CHUDZIK ,  Siddarth KRISHNAN ,  Wenyu ZHANG ,  Seshadri GANGULI ,  Naomi YOSHIDA ,  Lin DONG ,  Yixiong YANG ,  Liqi WU ,  Shih Chung CHEN

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66446 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78681

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.

公开(公告)号：US20170018624A1

公开(公告)日：2017-01-19

申请号：US15279257

申请日：2016-09-28

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Benjamin COLOMBEAU ,  Michael CHUDZIK

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/42392 ,  H01L21/02236 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/15 ,  H01L29/157 ,  H01L29/158 ,  H01L29/66742 ,  H01L29/78696

Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Abstract translation: 本文描述的实施例通常涉及用于水平门全周（hGAA）隔离的方法和装置。 可以在衬底上形成包括布置在交替堆叠的层中的不同材料的超晶格结构。 不同的材料可以是含硅材料和一种或多种III / V材料。 在一个实施例中，超晶格结构的至少一个层可以被氧化以形成邻近衬底的掩埋氧化物层。

公开(公告)号：US20210215664A1

公开(公告)日：2021-07-15

申请号：US16738629

申请日：2020-01-09

Applicant: Applied Materials, Inc.

Inventor： Mark J. SALY ,  Keenan Navarre WOODS ,  Joseph R. JOHNSON ,  Bhaskar Jyoti BHUYAN ,  William J. DURAND ,  Michael CHUDZIK ,  Raghav SREENIVASAN ,  Roger QUON

IPC: G01N33/487 ,  C12Q1/6869 ,  B82Y15/00

Abstract: Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.

公开(公告)号：US20200035822A1

公开(公告)日：2020-01-30

申请号：US16592362

申请日：2019-10-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi WOOD ,  Nam Sung KIM

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.