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88 条记录 (耗时 0.02 秒)

    Implementation of low power standby modes for integrated circuits
    11.
    发明授权
    Implementation of low power standby modes for integrated circuits 有权
    实现集成电路的低功耗待机模式

    公开(公告)号：US07498835B1

    公开(公告)日：2009-03-03

    申请号：US11268265

    申请日：2005-11-04

    申请人： Arifur Rahman ,  Sean W. Kao ,  Tim Tuan ,  Patrick J. Crotty ,  Jinsong Oliver Huang

    发明人： Arifur Rahman ,  Sean W. Kao ,  Tim Tuan ,  Patrick J. Crotty ,  Jinsong Oliver Huang

    IPC分类号： H03K19/173 ,  G11C5/14

    CPC分类号： H03K19/17772 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/148 ,  H03K19/0016 ,  H03K19/17784 ,  Y02D10/171 ,  Y02D50/20

    摘要： A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

    摘要翻译： PLD（200）包括功率管理单元（PMU 210），其响应于功率配置信号（PC）选择性地实现一个或多个不同的功率降低技术。 通过操纵PC信号，PMU可以独立地启用/禁用为CLB（101），IOB（102）和配置存储器单元（106）供电的各种电源电压电路（110,120,130）可以产生捕获信号， 导致存储在CLB的存储元件中的数据被捕获在配置存储单元中，和/或可以在电压供应电路之间切换配置存储单元的电源端子。 此外，响应于PC信号，PMU可以顺序地从多个可配置PLD部分中施加和去除电力，其中每个可配置部分可以包括任何数量的PLD资源。

    Low-swing interconnections for field programmable gate arrays
    13.
    发明授权
    Low-swing interconnections for field programmable gate arrays 有权
    用于现场可编程门阵列的低摆幅互连

    公开(公告)号：US07417454B1

    公开(公告)日：2008-08-26

    申请号：US11210498

    申请日：2005-08-24

    申请人： Arifur Rahman ,  Tim Tuan ,  Sean W. Kao

    发明人： Arifur Rahman ,  Tim Tuan ,  Sean W. Kao

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17784 ,  H03K17/002 ,  H03K17/693 ,  H03K19/1731 ,  H03K19/17728

    摘要： An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shifter circuits. For some embodiments, existing multiplexing circuit architectures provided within logic resources of various logic blocks of the configurable IC device may be used as level shifter circuits to increase the voltage swing of signals received into the blocks from the interconnect signal lines, and modified multiplexing circuit architectures provided within the logic resources may be used to reduce the voltage swing of signals output from the logic blocks onto the interconnect signal lines.

    摘要翻译： 公开了一种可以通过减少在器件的互连信号线上传输的信号的峰 - 峰电压摆幅而不包括额外的电平移位器电路来降低诸如FPGA的可配置IC器件的动态功耗的装置。 对于一些实施例，在可配置IC器件的各种逻辑块的逻辑资源内提供的现有多路复用电路架构可以用作电平移位器电路，以增加从互连信号线接收到块中的信号的电压摆幅，以及修改的多路复用电路架构 提供在逻辑资源内的信号可用于将从逻辑块输出的信号的电压摆幅减小到互连信号线上。

    On-chip programmable optical crossbar switch
    14.
    发明授权
    On-chip programmable optical crossbar switch 有权
    片上可编程光交叉开关

    公开(公告)号：US07310459B1

    公开(公告)日：2007-12-18

    申请号：US11259455

    申请日：2005-10-25

    申请人： Arifur Rahman

    发明人： Arifur Rahman

    IPC分类号： G02B6/12 ,  G02B6/26

    CPC分类号： G02B6/29395 ,  G02B6/12007 ,  G02B6/29343 ,  G02F2203/15 ,  G02F2203/58 ,  H04J14/02

    摘要： An integrated circuit has an optical waveguide configured to carry a plurality of optical channels, which in a particular embodiment are optical clock signals generated by an optical clock generator. The integrated circuit includes an optical crossbar having a first output, a second output, a first optical ring resonator, and a second optical ring resonator. In a further embodiment, the optical crossbar is an optical crossbar switch and an output path in the optical crossbar switch includes another tunable optical ring resonator and an intermediate waveguide, which allows isolating the output from any optical channel on the on-chip optical waveguide by tuning the first ring resonator to a first wavelength, and tuning the other ring resonator to another wavelength.

    摘要翻译： 集成电路具有配置成承载多个光通道的光波导，其在特定实施例中是由光时钟发生器产生的光时钟信号。 集成电路包括具有第一输出，第二输出，第一光环谐振器和第二光环谐振器的光交叉开关。 在另一实施例中，光学横杆是光学交叉开关，并且光学交叉开关中的输出路径包括另一个可调谐光环谐振器和中间波导，其允许通过片上光波导上的任何光通道将输出隔离 将第一环形谐振器调谐到第一波长，并将另一个环形谐振器调谐到另一个波长。

    Low voltage differential signaling systems and methods
    15.
    发明授权
    Low voltage differential signaling systems and methods 有权
    低压差分信号系统及方法

    公开(公告)号：US06639434B1

    公开(公告)日：2003-10-28

    申请号：US10266361

    申请日：2002-10-07

    申请人： Arifur Rahman

    发明人： Arifur Rahman

    IPC分类号： H03B100

    CPC分类号： H04L25/0272 ,  H04L25/028 ,  H04L25/45

    摘要： A low voltage differential signaling driver is disclosed that is capable of supporting many different LVDS standards or signal level requirements. The low voltage differential signaling driver has a programmable offset voltage and a programmable differential output voltage, which may be programmed independently.

    摘要翻译： 公开了能够支持许多不同的LVDS标准或信号电平要求的低压差动信号驱动器。 低电压差分信号驱动器具有可编程失调电压和可编程差分输出电压，可以独立编程。

    CIRCUITRY WITH ADAPTIVE MEMORY ASSISTANCE CAPABILITIES
    16.
    发明申请
    CIRCUITRY WITH ADAPTIVE MEMORY ASSISTANCE CAPABILITIES 审中-公开

    公开(公告)号：US20190042306A1

    公开(公告)日：2019-02-07

    申请号：US16019338

    申请日：2018-06-26

    申请人： Robert L. Pelt ,  Hong Wang ,  Arifur Rahman

    发明人： Robert L. Pelt ,  Hong Wang ,  Arifur Rahman

    IPC分类号： G06F9/48 ,  G06F9/445 ,  G06F9/52 ,  G06F12/0862 ,  G06F12/0871 ,  G06F12/126 ,  G06F8/41 ,  G06F17/50

    摘要： A system for running one or more applications is provided. Each application may require memory services that can be accelerated using configurable memory assistance circuits associated with different levels of a memory hierarchy. Integrated circuit design tools may be used to generate configuration data for programming the configurable memory assistance circuits. During compile time, the design tools may identify memory service patterns in a source code, match the identified memory service patterns to corresponding templates, parameterize the matching templates, and then synthesize the parameterized templates to produce the configuration data. During run time, a memory assistance scheduler may map the memory services required by each application to available memory assistance circuits in the system. The mapped memory assistance circuits are programmed by the configuration data to provide the desired memory service capability.

    Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
    18.
    发明授权
    Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP) 有权
    实现用于分布式DRAM系统级封装（SiP）的可编程存储器控制器的方法

    公开(公告)号：US08356138B1

    公开(公告)日：2013-01-15

    申请号：US11894346

    申请日：2007-08-20

    申请人： Chidamber R. Kulkarni ,  Arifur Rahman

    发明人： Chidamber R. Kulkarni ,  Arifur Rahman

    IPC分类号： G06F12/00

    CPC分类号： G06F17/5054

    摘要： A multi-port memory controller (MPMC) can be parameterized to selectively connect to different memory configurations. In particular, a programmable device that is combined with a DRAM in a die-stacked distributed memory in a single chip is provided with the programmable device forming the MPMC. The programmable device is parameterized to form a memory controller that can either aggregate or segment memory controller components to control different DRAM memory banks either together or separately. The aggregation or segmentation of the memory devices can be configured dynamically during operation of the programmable device.

    摘要翻译： 可以对多端口存储器控制器（MPMC）进行参数化，以选择性地连接到不同的存储器配置。 特别地，在单芯片中与芯片堆叠分布式存储器中的DRAM组合的可编程器件被提供有形成MPMC的可编程器件。 可编程设备被参数化以形成存储器控制器，其可以聚合或分段存储器控制器组件以一起或分开地控制不同的DRAM存储器组。 可以在可编程设备的操作期间动态地配置存储器设备的聚合或分段。

    DISPOSING UNDERFILL IN AN INTEGRATED CIRCUIT STRUCTURE
    20.
    发明申请
    DISPOSING UNDERFILL IN AN INTEGRATED CIRCUIT STRUCTURE 有权
    处理集成电路结构

    公开(公告)号：US20120139102A1

    公开(公告)日：2012-06-07

    申请号：US12958309

    申请日：2010-12-01

    申请人： Arifur Rahman

    发明人： Arifur Rahman

    IPC分类号： H01L23/48 ,  H01L21/60

    CPC分类号： H01L21/563 ,  H01L23/544 ,  H01L25/0655 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/73203

    摘要： In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured.

    摘要翻译： 在一个实施例中，提供了一种形成多芯片半导体器件的方法。 多个骰子安装在半导体衬底上，并且相邻骰子之间的相邻骰子被分开一段距离，在该距离处，相邻骰子中的第一个骰子将在底部填充期间与邻近骰子的凸缘的弯液面接触，以形成毛细管桥， 相邻的骰子。 焊接凸块被回流以将多个裸片的接触端子电连接到衬底的顶表面上的接触端子。 底部填充物沉积在多个骰子中的一个或多个骰子的一个或多个边缘上。 作为在相邻骰子之间形成的毛细管桥的结果，在相邻骰子的底表面和衬底的顶表面之间引起底部填充物的流动。 分配的底部填充物固化。