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    Power Prediction Systems, Circuitry and Methods
    11.
    发明公开
    Power Prediction Systems, Circuitry and Methods 审中-公开

    公开(公告)号：US20240095430A1

    公开(公告)日：2024-03-21

    申请号：US17902810

    申请日：2022-09-03

    Applicant: Arm Limited

    Inventor： Nicolas Christophe Hébert ,  Shidhartha Das

    IPC: G06F30/327 ,  G06F30/27 ,  G06F30/3308

    CPC classification number: G06F30/327 ,  G06F30/27 ,  G06F30/3308

    Abstract: According to one implementation of the present disclosure, a method includes: receiving, by a hardware design generation circuit, a plurality of input signals of a software workload on a processing unit; training a power prediction model based on a toggling of the input signals accumulated over a training interval range; determining, by the hardware design generation circuit, a plurality of prediction proxies and respective weightings for the plurality of prediction proxies based at least partially on the trained power prediction model, wherein the plurality of weighted prediction proxies correspond to a power output of the hardware design generation circuit; and generating an updated circuit design of the processing unit based on the power output.

    Refactoring mac operations
    12.
    发明授权
    Refactoring mac operations 有权

    公开(公告)号：US11922169B2

    公开(公告)日：2024-03-05

    申请号：US17674503

    申请日：2022-02-17

    Applicant: Arm Limited

    Inventor： Matthew Mattina ,  Shidhartha Das ,  Glen Arnold Rosendale ,  Fernando Garcia Redondo

    IPC: G06F9/38 ,  G06F7/487 ,  G06F7/544 ,  G06F9/30 ,  G06F17/16 ,  G06N3/06

    CPC classification number: G06F9/3893 ,  G06F7/4876 ,  G06F7/5443 ,  G06F9/30014 ,  G06F17/16 ,  G06N3/06

    Abstract: A method and apparatus for performing refactored multiply-and-accumulate operations is provided. A summing array includes a plurality of non-volatile memory elements arranged in columns. Each non-volatile memory element in the summing array is programmed to a high resistance state or a low resistance state based on weights of a neural network. The summing array is configured to generate a summed signal for each column based, at least in part, on a plurality of input signals. A multiplying array is coupled to the summing array, and includes a plurality of non-volatile memory elements. Each non-volatile memory element in the multiplying array is programmed to a different conductance level based on the weights of the neural network. The multiplying array is configured to generate an output signal based, at least in part, on the summed signals from the summing array.

    DIGITAL SAMPLING TECHNIQUES
    15.
    发明申请
    DIGITAL SAMPLING TECHNIQUES 有权

    公开(公告)号：US20220399895A1

    公开(公告)日：2022-12-15

    申请号：US17344390

    申请日：2021-06-10

    Applicant: Arm Limited

    Inventor： Shidhartha Das ,  Yunpeng Cai ,  Supreet Jeloka

    IPC: H03L7/099 ,  H03L7/187 ,  H03L7/081 ,  H03L7/199 ,  H03L7/091

    Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

    Hybrid memory artificial neural network hardware accelerator
    16.
    发明授权
    Hybrid memory artificial neural network hardware accelerator 有权

    公开(公告)号：US11468305B2

    公开(公告)日：2022-10-11

    申请号：US16822640

    申请日：2020-03-18

    Applicant: Arm Limited

    Inventor： Urmish Ajit Thakker ,  Shidhartha Das ,  Ganesh Suryanarayan Dasika

    IPC: G06N3/063 ,  G06F12/06 ,  G06N3/04

    Abstract: The present disclosure advantageously provides a hybrid memory artificial neural network hardware accelerator that includes a communication bus interface, a static memory, a non-refreshed dynamic memory, a controller and a computing engine. The static memory stores at least a portion of an ANN model. The ANN model includes an input layer, one or more hidden layers and an output layer, ANN basis weights, input data and output data. The non-refreshed dynamic memory is configured to store ANN custom weights for the input, hidden and output layers, and output data. For each layer or layer portion, the computing engine generates the ANN custom weights based on the ANN basis weights, stores the ANN custom weights in the non-refreshed dynamic memory, executes the layer or layer portion, based on inputs and the ANN custom weights, to generate layer output data, and stores the layer output data.

    Cache apparatus and method that facilitates a reduction in energy consumption through use of first and second data arrays
    17.
    发明授权
    Cache apparatus and method that facilitates a reduction in energy consumption through use of first and second data arrays 有权

    公开(公告)号：US11036639B2

    公开(公告)日：2021-06-15

    申请号：US15864062

    申请日：2018-01-08

    Applicant: ARM Limited

    Inventor： Ricardo Daniel Queiros Alves ,  Nikos Nikoleris ,  Shidhartha Das ,  Andreas Lars Sandberg

    IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0862 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/0888

    Abstract: A cache apparatus is provided comprising a data storage structure providing N cache ways that each store data as a plurality of cache blocks. The data storage structure is organised as a plurality of sets, where each set comprises a cache block from each way, and further the data storage structure comprises a first data array and a second data array, where at least the second data array is set associative. A set associative tag storage structure stores a tag value for each cache block, with that set associative tag storage structure being shared by the first and second data arrays. Control circuitry applies an access likelihood policy to determine, for each set, a subset of the cache blocks of that set to be stored within the first data array. Access circuitry is then responsive to an access request to perform a lookup operation within an identified set of the set associative tag storage structure overlapped with an access operation to access within the first data array the subset of the cache blocks for the identified set. In the event of a hit condition being detected that identifies a cache block present in the first data array, that access request is then processed using the cache block accessed within the first data array. If instead a hit condition is detected that identifies a cache block absent in the first data array, then a further access operation is performed to access the identified cache block within a selected way of the second data array. Such a cache structure provides a high performance and energy efficient mechanism for storing cached data.

    Apparatus and method for processing a received input signal containing a sequence of data blocks
    18.
    发明授权
    Apparatus and method for processing a received input signal containing a sequence of data blocks 有权

    公开(公告)号：US10797915B2

    公开(公告)日：2020-10-06

    申请号：US15761212

    申请日：2016-09-12

    Applicant: ARM LIMITED

    Inventor： Paul Nicholas Whatmough ,  Shidhartha Das

    IPC: H04L25/06 ,  H04L25/49 ,  H04L25/03 ,  H04W4/80

    Abstract: An apparatus and method are provided for processing a received input signal comprising a sequence of data blocks. Counter circuitry within the apparatus is arranged to receive a digital representation of the input signal, and for each data block generates a count value indicative of occurrences of a property of the digital representation (for example a rising edge or a falling edge) during an associated data block transmission period. Quantization circuitry then maps each count value to a soft decision value from amongst a predetermined set of soft decision values, where the number of soft decision values in the predetermined set exceeds a number of possible data values of the data block. The output circuitry then generates a digital output signal in dependence on the soft decision values. Such an apparatus has been found to provide a low power technique for a receiver, whilst still enabling the improved sensitivity benefits of using soft decisions to be achieved, and allows the apparatus to be constructed using all digital components.

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