公开(公告)号：US20180019263A1

公开(公告)日：2018-01-18

申请号：US15545817

申请日：2016-04-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong KONG ,  Jun CHENG ,  Xiaodi LIU

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L29/45 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L27/124 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  G02F2201/123 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: The embodiments of present disclosure disclose an array substrate, a method for manufacturing the array substrate, and a display device. The method includes forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.

公开(公告)号：US20180011356A1

公开(公告)日：2018-01-11

申请号：US15547410

申请日：2016-04-15

Applicant: BOE Technology Group Co, Ltd.

Inventor： Xiangyong KONG

IPC: G02F1/1368 ,  G02F1/1343 ,  H01L27/12

Abstract: The present disclosure discloses an array substrate, a display device and manufacturing methods thereof. The array substrate comprises: a base, a gate metal layer, an active layer, a source/drain metal layer, and a pixel electrode layer, wherein the array substrate has a storage capacitor region; in the storage capacitor region, the gate metal layer, the active layer, the source/drain metal layer and the pixel electrode layer comprise respective patterns; wherein, the projections of the gate metal layer storage pattern, the active layer storage pattern, the source/drain metal layer storage pattern, and the pixel electrode layer storage pattern on the base at least partially overlap, and the pixel electrode layer storage pattern is electrically connected to the gate metal layer storage pattern to form a first electrode of the storage capacitor, the active layer storage pattern is electrically connected to the source/drain metal layer storage pattern to form a second electrode.

公开(公告)号：US20170194448A1

公开(公告)日：2017-07-06

申请号：US15313141

申请日：2016-03-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong KONG ,  Lung Pao HSIN ,  Jun CHENG

IPC: H01L29/45 ,  H01L21/311 ,  H01L29/417 ,  H01L21/4757 ,  H01L29/66 ,  H01L21/768 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L21/31144 ,  H01L21/47573 ,  H01L21/76802 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

Abstract: Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a base substrate, a first electrode pattern, a second electrode pattern, and an active layer pattern disposed on the base substrate, a first electrode protection pattern coating the first electrode pattern, and a second electrode protection pattern coating the second electrode pattern. The active layer pattern is disposed between the first electrode pattern and the second electrode pattern. The first electrode protection pattern and the second electrode protection pattern are connected to two sides of the active layer pattern, respectively. The problem that, the active layer pattern cannot be connected to the first electrode pattern and the second electrode pattern due to the surface oxidation, when the first electrode pattern and the second electrode pattern adopt material with low resistance characteristic, is avoided, thus increasing the product yield.

公开(公告)号：US20160013060A1

公开(公告)日：2016-01-14

申请号：US14429279

申请日：2014-07-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong KONG ,  Hongda SUN

IPC: H01L21/283 ,  H01L29/66 ,  H01L21/311 ,  H01L29/45 ,  H01L27/32 ,  H01L29/51 ,  H01L29/423 ,  H01L29/417 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49

CPC classification number: H01L21/283 ,  G02F2001/136295 ,  H01L21/31144 ,  H01L21/77 ,  H01L27/1237 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/3244 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/786

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are provided. The array substrate comprises: a base substrate and an electrode arranged on the base substrate. The electrode comprises: an aluminum layer or an aluminum alloy layer on the base substrate; and a first barrier layer arranged on the aluminum layer or the aluminum alloy layer and configured for preventing the aluminum layer or the aluminum alloy layer from producing hillocks. The array substrate can eliminate bad phenomenon that the metal aluminum or aluminum alloy formed on the base substrate produces hillocks when subjected to high temperature.

Abstract translation: 提供薄膜晶体管及其制造方法，阵列基板及其制造方法以及显示装置。 阵列基板包括：基底基板和设置在基底基板上的电极。 所述电极包括：在所述基底基板上的铝层或铝合金层; 以及布置在所述铝层或所述铝合金层上并且被配置为防止所述铝层或所述铝合金层产生小丘的第一阻挡层。 阵列基板可以消除在高温下形成在基底基板上的金属铝或铝合金产生小丘的不良现象。