公开(公告)号：US20170206838A1

公开(公告)日：2017-07-20

申请号：US15321543

申请日：2016-03-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Cuili GAI ,  Liye DUAN ,  Xiaodi LIU

IPC: G09G3/3258

CPC classification number: G09G3/3258 ,  G09G3/3225 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0861 ,  G09G2310/0262 ,  G09G2320/0233 ,  G09G2320/043 ,  G09G2320/045

Abstract: Embodiments of the present disclosure provide a pixel driving circuit and a pixel driving method. The pixel driving circuit comprises a driving transistor, a storage capacitor, a light-emitting device, a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor and a fifth switch transistor. The pixel driving circuit and the pixel driving method are implemented such that a driving current generated by the driving transistor is relevant to a working voltage provided by a first power supply terminal, an activation voltage of the light-emitting device, a working voltage of the light-emitting device upon emitting light and a data voltage, yet irrelevant to a threshold voltage of the driving transistor, thereby refraining the driving current flowing through the light-emitting device from influence exerted by the non-uniformity and drifting of the threshold voltage of the driving transistor, and in turn effectively improving the uniformity of the driving current flowing through the light-emitting device. When the activation voltage of the light-emitting device increases with the aging of the light-emitting device, the pixel driving circuit and the pixel driving method enable the driving current flowing through the light-emitting device to increase, thereby compensating for attenuation of the display luminance caused by the aging of the light-emitting device.

公开(公告)号：US20160247833A1

公开(公告)日：2016-08-25

申请号：US14443542

申请日：2014-09-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Cuili GAI ,  Xiaodi LIU

IPC: H01L27/12

CPC classification number: H01L27/1237 ,  G02F1/136204 ,  H01L27/0248 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/42384 ,  H01L2029/42388

Abstract: An array substrate includes a display area and a driving area; thin film transistors in the display area and the driving area are provided with insulation layers between gate electrodes and active layers, and the thickness of the insulation layer of the thin film transistor in the driving area is larger than the thickness of the insulation layer of the thin film transistor in the display area. The present invention has the beneficial effects that when electrostatic discharge occurs between the gate electrode and the source/drain electrodes of the driving area, the breakdown of the insulation layer can be prevented, thereby resulting in no short circuit of the gate electrode and the source/drain electrodes; meanwhile, adverse effects such as a reduced migration rate and threshold voltage drift of the thin film transistor in the display area will not be caused.

Abstract translation: 阵列基板包括显示区域和驱动区域; 显示区域和驱动区域中的薄膜晶体管在栅电极和有源层之间设置有绝缘层，并且驱动区域中的薄膜晶体管的绝缘层的厚度大于绝缘层的厚度 薄膜晶体管在显示区域。 本发明具有如下效果：当驱动区域的栅电极和源极/漏电极之间发生静电放电时，可以防止绝缘层的击穿，从而不会使栅电极和源极短路 /漏电极; 同时，不会引起诸如显示区域中的薄膜晶体管的迁移率降低和阈值电压漂移等不良影响。

公开(公告)号：US20150318383A1

公开(公告)日：2015-11-05

申请号：US14800089

申请日：2015-07-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaodi LIU ,  Li SUN ,  Haijing CHEN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L21/467 ,  H01L21/477 ,  H01L29/786 ,  H01L21/027

CPC classification number: H01L29/78693 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02631 ,  H01L21/0273 ,  H01L21/441 ,  H01L21/467 ,  H01L21/477 ,  H01L29/66969 ,  H01L29/78618

Abstract: Embodiments of the disclosed technology provide an amorphous oxide thin film transistor (TFT), a method for preparing an amorphous oxide TFT, and a display panel. The amorphous oxide thin film transistor includes: a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode and a drain electrode. The semiconductor active layer comprises a channel layer and an ohmic contact layer, and the channel layer has a greater content of oxygen than the ohmic contact layer; the channel layer contacts the gate insulating layer, and the ohmic contact layer comprises two separated ohmic contact regions, one of which contacts the source electrode and the other of which contacts the drain electrode.

Abstract translation: 所公开技术的实施例提供无定形氧化物薄膜晶体管（TFT），制备无定形氧化物TFT的方法和显示面板。 无定形氧化物薄膜晶体管包括：栅极，栅极绝缘层，半导体有源层，源极和漏极。 半导体有源层包括沟道层和欧姆接触层，并且沟道层具有比欧姆接触层更大的氧含量; 沟道层接触栅极绝缘层，欧姆接触层包括两个分离的欧姆接触区域，其中一个接触源极电极，另一个接触漏极电极。

公开(公告)号：US20170104102A1

公开(公告)日：2017-04-13

申请号：US14905512

申请日：2015-08-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaodi LIU ,  Gang WANG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L27/12 ,  H01L21/385

CPC classification number: H01L29/7869 ,  H01L21/385 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78696

Abstract: Embodiments of the present invention disclose a thin film transistor and an array substrate, manufacturing methods thereof, and a display device, which relate to the field of display technology, and can improve drifting of a threshold voltage of a thin film transistor and enhance the stability and reliability of an array substrate. The thin film transistor comprises an active layer and a gate insulating layer, wherein the material of the active layer is a metal oxide semiconductor, and during forming the thin film transistor, the gate insulating layer conveys oxygen to the active layer so as to reduce an interface state density and a movable impurity concentration of a. contact interface between the active layer and the gate insulating layer.

公开(公告)号：US20160035753A1

公开(公告)日：2016-02-04

申请号：US14429165

申请日：2014-06-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaodi LIU ,  Gang WANG

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1214 ,  H01L27/1233 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/786 ,  H01L29/78696

Abstract: The present invention provides a complementary thin film transistor and a manufacturing method thereof, an array substrate and a display apparatus, relates to the field of manufacturing technology of thin film transistor, and can solve the problem that active layer materials of first and second thin film transistors in a complementary thin film transistor of the prior art have influence with each other. The manufacturing method of the present invention comprises steps of: forming a pattern comprising an active layer of a first thin film transistor and a protective layer on a base by a patterning process, and the protective layer is at least located above the active layer of the thin film transistor; and forming a pattern of an active layer of a second thin film transistor on the base subjected to above step by a patterning process. The present invention may be applied to various circuits and systems.

Abstract translation: 本发明提供了一种互补薄膜晶体管及其制造方法，阵列基板和显示装置，涉及薄膜晶体管的制造技术领域，并且可以解决第一和第二薄膜的有源层材料的问题 现有技术的互补薄膜晶体管中的晶体管彼此具有影响。 本发明的制造方法包括以下步骤：通过图案化工艺在基底上形成包括第一薄膜晶体管的有源层和保护层的图案，并且保护层至少位于 薄膜晶体管; 以及通过图案化工艺在经过上述步骤的基底上形成第二薄膜晶体管的有源层的图案。 本发明可以应用于各种电路和系统。

公开(公告)号：US20180083050A1

公开(公告)日：2018-03-22

申请号：US15826184

申请日：2017-11-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Cuili GAI ,  Xiaodi LIU

IPC: H01L27/12 ,  G02F1/1362 ,  H01L27/02

CPC classification number: H01L27/1237 ,  G02F1/136204 ,  H01L27/0248 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/42384 ,  H01L2029/42388

Abstract: The present invention provides a manufacturing method of an array substrate, comprising a step of forming insulation layers in a driving area and a display area of the array substrate, wherein thin film transistors are provided in both the display area and the driving area; the insulation layers are arranged between gate electrodes and active layers of the thin film transistors. A thickness of the insulation layer of the thin film transistor in the driving area is larger than a thickness of the insulation layer of the thin film transistor in the display area.

公开(公告)号：US20180019263A1

公开(公告)日：2018-01-18

申请号：US15545817

申请日：2016-04-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong KONG ,  Jun CHENG ,  Xiaodi LIU

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L29/45 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L27/124 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  G02F2201/123 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: The embodiments of present disclosure disclose an array substrate, a method for manufacturing the array substrate, and a display device. The method includes forming a pixel electrode layer, a gate metal layer, and a source/drain metal layer on a base substrate, the pixel electrode layer including a first connection part pattern, the gate metal layer including a second connection part pattern, the source/drain metal layer including a third connection part pattern, wherein the first connection part pattern and the second connection part pattern overlap, and a portion of the first connection part pattern extending beyond the second connection part pattern is electrically connected with the third connection part pattern through a first via hole.

公开(公告)号：US20150325605A1

公开(公告)日：2015-11-12

申请号：US14416872

申请日：2014-05-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaodi LIU ,  Gang WANG

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/383 ,  H01L29/786 ,  H01L21/477

CPC classification number: H01L27/1288 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/383 ,  H01L21/477 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/7869

Abstract: A complementary thin film transistor driving back plate and a preparing method thereof, and a display device are disclosed. The preparing method comprises: forming a lower electrode (102) on a base substrate (101); sequentially disposing a continuously grown dielectric layer (103), a semiconductor layer (104), and a diffusion protection layer (105); sequentially forming a no-photoresist region (107), an N-type thin film transistor preparation region (108), and a P-type thin film transistor preparation region (109); removing a photoresist layer (114) of the N-type thin film transistor preparation region (108); removing a diffusion protection layer (105) of the N-type thin film transistor preparation region (105); removing a photoresist layer (114) of the P-type thin film transistor preparation region (109); performing an oxidation treatment to the base substrate (101); disposing a passivation layer (111) on the base substrate (101); and forming an upper electrode (113) on the passivation layer (111).

Abstract translation: 互补薄膜晶体管驱动背板及其制备方法和显示装置。 制备方法包括：在基底（101）上形成下电极（102）; 顺序地设置连续生长的介电层（103），半导体层（104）和扩散保护层（105）; 依次形成无光致抗蚀剂区域（107），N型薄膜晶体管制备区域（108）和P型薄膜晶体管制备区域（109）; 去除所述N型薄膜晶体管制备区域（108）的光致抗蚀剂层（114）; 去除N型薄膜晶体管制备区域（105）的扩散保护层（105）; 去除P型薄膜晶体管制备区域（109）的光致抗蚀剂层（114）; 对所述基底基板进行氧化处理; 在所述基底基板（101）上设置钝化层（111）; 以及在所述钝化层（111）上形成上电极（113）。

公开(公告)号：US20170207346A1

公开(公告)日：2017-07-20

申请号：US15329180

申请日：2015-11-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong KONG ,  Xiaming ZHU ,  Xiaodi LIU

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/78633 ,  H01L21/28 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66 ,  H01L29/66969 ,  H01L29/76 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present disclosure discloses in embodiments a thin film transistor and a manufacturing method thereof, an array substrate. The thin film transistor comprises: a base substrate, an active layer, a source, a gate, and a drain. Two ends of the active layer are connected to the source and the drain, respectively. The gate comprises a top gate and a bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate comprising a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate side portion extending from the top gate top portion towards the base substrate. The active layer is sandwiched between the top gate top portion and the bottom gate. A sidewall of the active layer is at least partially surrounded by the top gate side portion.