公开(公告)号：US20210201840A1

公开(公告)日：2021-07-01

申请号：US16084027

申请日：2018-04-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Liugang Zhou ,  Haoliang Zheng ,  Yaoqiu Jing ,  Mingfu Han ,  Seungwoo Han

IPC: G09G3/36

Abstract: The present disclosure is related to a driving circuit of a display panel. The driving circuit may include a turn-on voltage adjusting circuit. The turn-on voltage adjusting circuit may include a control subcircuit and a switching and voltage division subcircuit. The switching and voltage division subcircuit may include a switching subcircuit and a basic voltage division subcircuit. The switching subcircuit may be configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node.

公开(公告)号：US20200258463A1

公开(公告)日：2020-08-13

申请号：US15768309

申请日：2017-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seungwoo Han ,  Guangliang Shang ,  Haoliang Zheng ,  Xing Yao ,  Zhichong Wang ,  Mingfu Han ,  Lijun Yuan ,  Yunsik IM ,  Jing Lv ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28

Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

公开(公告)号：US20180315388A1

公开(公告)日：2018-11-01

申请号：US15565756

申请日：2017-03-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Guangliang Shang

IPC: G09G3/36 ,  H01L27/12 ,  H01L29/786

CPC classification number: G09G3/3677 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2202/10 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/36 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0404 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2310/0205 ,  G09G2310/021 ,  G09G2320/043 ,  G09G2320/045 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869

Abstract: The present application discloses an array substrate comprising a plurality of gate lines and a plurality of data lines crossing over each other thereby defining an array of a plurality of sub-pixel areas, each sub-pixel area comprising a pixel electrode and multiple switching transistors having respective gate electrodes coupled to multiple different gate lines, wherein the pixel electrode is configured to be charged by a data signal from a data line only with all the multiple switching transistors being turned on concurrently during a pixel electrode charging period by an effective voltage level applied on the respective multiple different gate lines.

公开(公告)号：US20180301200A1

公开(公告)日：2018-10-18

申请号：US15520191

申请日：2016-11-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seungwoo Han ,  Mingfu Han ,  Haoliang Zheng ,  Xing Yao ,  Hyunsic Choi

IPC: G11C19/28 ,  G09G3/36

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2330/06

Abstract: The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.

公开(公告)号：US10096374B2

公开(公告)日：2018-10-09

申请号：US15539220

申请日：2016-11-01

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Seungwoo Han ,  Haoliang Zheng ,  Xing Yao ,  Mingfu Han ,  Hyunsic Choi ,  Yunsik Im ,  Yinglong Huang ,  Jungmok Jun ,  Xue Dong

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

公开(公告)号：US10002675B2

公开(公告)日：2018-06-19

申请号：US15504119

申请日：2016-08-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Xing Yao ,  Hyunsic Choi ,  Guangliang Shang ,  Mingfu Han ,  Yunsik Im ,  Jungmok Jun ,  Xue Dong

IPC: G09G5/00 ,  G11C19/28 ,  G09G3/36 ,  G11C19/18 ,  H01L27/12

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251

Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.

公开(公告)号：US09685134B2

公开(公告)日：2017-06-20

申请号：US14777587

申请日：2015-03-19

Applicant: Boe Technology Group Co., Ltd.

Inventor： Yuanbo Zhang ,  Seungwoo Han ,  Yunsik Im

IPC: G09G3/36 ,  G06F3/038 ,  G09G5/00 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2330/06 ,  G11C19/28

Abstract: The present invention provides a shift register unit, a gate driving circuit and a display device, which belongs to the field of display technology. The shift register unit of the present invention comprises: an input module, a pull-up module, a pull-down control module, a pull-down module, a reset module and a discharge module.

公开(公告)号：US12302678B2

公开(公告)日：2025-05-13

申请号：US18648499

申请日：2024-04-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ming Yang ,  Seungwoo Han ,  Zhuo Li ,  Dingchang Zhang ,  Xuan Feng ,  Hui Zhang ,  Liwei Liu

IPC: H10H20/80 ,  G09G3/32 ,  G09G3/3233 ,  H01L25/16 ,  H10D86/40 ,  H10D86/60 ,  H10H20/857

Abstract: A pixel circuit includes a pixel driving circuit and a bonding unit connected thereto. The bonding unit includes a first bonding terminal group and at least one second bonding terminal group that are arranged in parallel, and the first bonding terminal group and a second bonding terminal group are configured to bond light-emitting devices. The first bonding terminal group includes a first terminal and a second terminal, and the second bonding terminal group includes a third terminal and a fourth terminal. The first terminal and the third terminal are connected, and are both connected to the pixel driving circuit; the second terminal and the fourth terminal are connected, and are both connected to a set voltage signal line.

公开(公告)号：US12277893B2

公开(公告)日：2025-04-15

申请号：US17620206

申请日：2020-12-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Haoliang Zheng ,  Minghua Xuan

IPC: G09G3/20 ,  G09G3/32 ,  G11C19/18 ,  G11C19/28

Abstract: A shift register includes: an input circuit for transmitting an input signal to a first node under control of a first clock signal, and for transmitting the first clock signal to the second node under control of a level of the first node; a control circuit for transmitting a second power supply signal to the first node under control of a level of the second node and a second clock signal, for transmitting the second clock signal to the third node under control of a level of the fourth node and/or the first; a pull-down control circuit; and an output circuit for transmitting the fourth power supply signal or the third power supply signal to the signal output terminal. The pull-down control circuit controls a level of the fifth node regardless of the first clock signal.

公开(公告)号：US12254841B2

公开(公告)日：2025-03-18

申请号：US18274470

申请日：2021-12-20

Applicant: BOE Technology Group Co., Ltd.

Inventor： Haoliang Zheng ,  Yan Qu ,  Dongni Liu ,  Li Xiao ,  Jiao Zhao ,  Xiaorong Cui ,  Seungwoo Han ,  Minghua Xuan

IPC: G09G3/3275 ,  G09G3/3266

Abstract: A display substrate a driving method therefor, and a display apparatus. The display substrate comprises: M rows and N columns of sub-pixels, N data signal lines and a data reset circuit, wherein at least one sub-pixel comprises a pixel circuit; an ith data signal line is connected to pixel circuits in an ith column, where M≥1, N≥1, and 1≤i≤N; and the data reset circuit is electrically connected to a data reset control end, a data initial signal end and the N data signal lines, and is configured to provide a signal of the data initial signal end to the N data signal lines under the control of the data reset control end.