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公开(公告)号：US07960267B2
公开(公告)日：2011-06-14
申请号：US12414778
申请日：2009-03-31
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/7847 , H01L29/7881
摘要： A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.
摘要翻译： 在半导体层上制造半导体器件的方法包括：在半导体层上形成栅极电介质; 在所述栅极电介质上形成栅极材料层; 蚀刻栅极材料层以形成选择栅极; 形成在所述选择栅极上方和所述半导体层的一部分上方延伸的存储层; 在所述存储层上沉积非晶硅层; 蚀刻非晶硅层以形成控制栅极; 并对半导体器件进行退火以使非晶硅层结晶。
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12.发明授权Method of forming a semiconductor device featuring a gate stressor and semiconductor device 有权形成具有栅极应力和半导体器件的半导体器件的方法公开(公告)号：US07960243B2
公开(公告)日：2011-06-14
申请号：US11756231
申请日：2007-05-31
IPC分类号： H01L21/76 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823828 , H01L29/7833 , H01L29/7845
摘要： A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
摘要翻译： 半导体器件（10）形成在半导体层（12）中。 在半导体层之上形成栅堆叠（16,18），并且包括第一层上的第一导电层（22）和第二层（24）。 第一层比第二层更具导电性并且为植入物提供更多的停止力。 物种（46）被植入第二层。 源极/漏极区域（52）形成在栅极堆叠的相对侧上的半导体层中。 栅极堆叠在注入步骤之后被加热，以使栅极堆叠在栅叠层下方的区域中的半导体层中施加应力。
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公开(公告)号：US09343314B2
公开(公告)日：2016-05-17
申请号：US14291359
申请日：2014-05-30
IPC分类号： H01L21/28 , H01L29/788 , H01L27/115 , H01L29/792
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/28273 , H01L21/28282 , H01L27/11534 , H01L27/11573 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/7883 , H01L29/792
摘要： A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.
摘要翻译： 一种制造分离栅极非易失性存储器（NVM）的方法包括在衬底上形成电荷存储层，沉积第一导电层和沉积覆盖层。 将这些层图案化以形成控制栅叠层。 第二导电层沉积在衬底上并被图案化以将第二导电层的第一部分留在控制栅极堆叠的一部分上并且邻近控制栅极堆叠的第一侧。 第二导电层和控制栅极堆叠的第一部分被平坦化以从第二导电层的第一部分留出虚拟选择栅极，其中第一导电层的剩余部分的顶表面相对于顶部 虚拟选通门的表面。 虚拟选择栅极被包括金属的选择栅极替代。
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公开(公告)号：US09202930B2
公开(公告)日：2015-12-01
申请号：US13111580
申请日：2011-05-19
IPC分类号： H01L29/788 , H01L29/423 , H01L29/66 , B82Y10/00 , G11C16/04
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0425 , H01L29/42332 , H01L29/66825
摘要： A method of making a non-volatile memory cell includes forming a plurality of discrete storage elements. A tensile dielectric layer is formed among the discrete storage elements and provides lateral tensile stress to the discrete storage elements. A gate is formed over the discrete storage elements.
摘要翻译： 制造非易失性存储单元的方法包括形成多个离散存储元件。 在离散存储元件之间形成拉伸介电层，并向分立存储元件提供横向拉伸应力。 在离散存储元件上形成栅极。
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15.发明授权Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner 有权浅沟槽隔离用于结合侧墙和底衬的SOI结构公开(公告)号：US08236638B2
公开(公告)日：2012-08-07
申请号：US11788184
申请日：2007-04-18
申请人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
发明人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/76
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/66477 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.
摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210） 其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。
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公开(公告)号：US09379222B2
公开(公告)日：2016-06-28
申请号：US14291320
申请日：2014-05-30
IPC分类号： H01L29/66 , H01L29/423 , H01L29/49 , H01L21/28 , H01L21/3213 , H01L21/306 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28035 , H01L21/28282 , H01L21/30625 , H01L21/32133 , H01L29/42332 , H01L29/42344 , H01L29/4916 , H01L29/66545 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： Making a non-volatile memory (NVM) structure uses a semiconductor substrate. One embodiment includes forming a select gate structure including a first dummy material on the semiconductor substrate and forming a control gate structure including a second dummy material on the semiconductor substrate, where the first dummy material is different from the second dummy material. The embodiment also includes replacing the first dummy material with metal and replacing the second dummy material with polysilicon.
摘要翻译： 制造非易失性存储器（NVM）结构使用半导体衬底。 一个实施例包括在半导体衬底上形成包括第一虚拟材料的选择栅极结构，并在半导体衬底上形成包括第二虚拟材料的控制栅极结构，其中第一虚拟材料与第二虚拟材料不同。 该实施例还包括用金属代替第一虚拟材料并用多晶硅代替第二虚拟材料。
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公开(公告)号：US09331160B2
公开(公告)日：2016-05-03
申请号：US13970796
申请日：2013-08-20
IPC分类号： H01L21/336 , H01L29/788 , H01L29/423 , H01L29/792 , H01L29/66
CPC分类号： H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the gate. For some disclosed embodiments, a select gate is formed before a control gate. For other disclosed embodiments, the control gate is formed before the select gate. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.
摘要翻译： 具有间隙保护区的分离式非易失性存储器（NVM）单元以及相关的制造方法被公开。 在衬底上形成用于分闸NVM单元的栅极之后，在栅极附近形成掺杂区域。 然后去除掺杂区域的第一部分以留下形成与栅极相邻的间隙保护区的掺杂区域的第二部分。 对于一些公开的实施例，在控制门之前形成选择栅极。 对于其他公开的实施例，控制栅极形成在选择栅极之前。 间隙保护区可以例如使用蚀刻处理步骤来形成，以去除掺杂区域的期望部分，并且在该蚀刻处理步骤期间也可以使用间隔物来保护间隙保护区。 还公开了相关的NVM系统。
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18.发明授权Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner 有权浅沟槽隔离用于结合侧墙和底衬的SOI结构公开(公告)号：US08766362B2
公开(公告)日：2014-07-01
申请号：US13548304
申请日：2012-07-13
申请人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
发明人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/66477 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.
摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210） 其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。
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公开(公告)号：US20130109141A1
公开(公告)日：2013-05-02
申请号：US13282210
申请日：2011-10-26
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823493 , H01L21/823412 , H01L21/823807 , H01L21/823892
摘要： A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.
摘要翻译： 第一晶体管和第二晶体管形成有不同的阈值电压。 第一栅极形成在用于第一晶体管的衬底的第一区域上，并且在第二区域上形成用于第二晶体管的第二栅极。 第一个区域被屏蔽。 通过在掩蔽第一区域的同时通过第二栅极注入来调节第二晶体管的阈值电压。 电流电极区域形成在第二栅极的相对侧上的第一栅极和电流电极区域的相对侧上。
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公开(公告)号：US20150054048A1
公开(公告)日：2015-02-26
申请号：US13970796
申请日：2013-08-20
IPC分类号： H01L29/423 , H01L29/792 , H01L29/66 , H01L29/788
CPC分类号： H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the select gate. For some disclosed embodiments, a select gate is formed before a control gate for the split-gate NVM cell. For other disclosed embodiments, the control gate is formed before the select gate for the split-gate NVM cell. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.
摘要翻译： 具有间隙保护区的分离式非易失性存储器（NVM）单元以及相关的制造方法被公开。 在衬底上形成用于分闸NVM单元的栅极之后，在栅极附近形成掺杂区域。 然后去除掺杂区域的第一部分以留下形成与选择栅极相邻的间隙保护区的掺杂区域的第二部分。 对于一些公开的实施例，在用于分闸门NVM单元的控制栅极之前形成选择栅极。 对于其他公开的实施例，控制栅极形成在分闸门NVM单元的选择栅极之前。 间隙保护区可以例如使用蚀刻处理步骤来形成，以去除掺杂区域的期望部分，并且在该蚀刻处理步骤期间也可以使用间隔物来保护间隙保护区。 还公开了相关的NVM系统。
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