公开(公告)号：US06184149B2

公开(公告)日：2001-02-06

申请号：US08918315

申请日：1997-08-26

申请人： Li-Chih Chao ,  Yuan-Chang Huang

发明人： Li-Chih Chao ,  Yuan-Chang Huang

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L22/20

摘要： The present invention provides a method for monitoring a self-aligned contact (SAC) etching process. A wafer with an oxide layer serves as an oxide control wafer. The oxide layer is formed on the substrate. The oxide control wafer and a SAC wafer with SAC structure are simultaneously treated with a SAC etching process in an etching chamber with the same etching recipe. A contact hole is formed by etching the oxide layer of the oxide control wafer after the SAC etching process. The depth of a profile transition point and the depth of etching stop for the oxide control wafer can be observed by cross-section SEM. The profile transition depth in the oxide control wafer corresponds to the etching thickness of SiN corner loss in the SAC wafer. Therefore, the profile transition depth and the depth of etching stop in the oxide control wafer can be used to monitor the etching chamber condition.

摘要翻译： 本发明提供一种用于监测自对准接触（SAC）蚀刻工艺的方法。 具有氧化物层的晶片用作氧化物控制晶片。 在基板上形成氧化物层。 具有SAC结构的氧化物控制晶片和SAC晶片在蚀刻室中用SAC蚀刻工艺同时用相同的蚀刻配方进行处理。 在SAC蚀刻工艺之后通过蚀刻氧化物控制晶片的氧化物层形成接触孔。 通过横截面SEM可以观察到轮廓转变点的深度和氧化物控制晶片的蚀刻停止深度。 氧化物控制晶片中的轮廓转移深度对应于SAC晶片中SiN角损失的蚀刻厚度。 因此，可以使用氧化物控制晶片中的轮廓转移深度和蚀刻停止深度来监测蚀刻室状况。

公开(公告)号：US6107206A

公开(公告)日：2000-08-22

申请号：US152350

申请日：1998-09-14

申请人： Li-Chih Chao ,  Chao-Cheng Chen

发明人： Li-Chih Chao ,  Chao-Cheng Chen

IPC分类号： H01L21/3065 ,  H01L21/762 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3065 ,  H01L21/76232

摘要： A method of etching closely spaced trenches in a silicon body wherein a masked silicon body is introduced into a plasma etching apparatus. An object having an exposed silicon surface that is consumable by a plasma environment is provided in the apparatus. A reactive plasma environment is established in the apparatus which removes silicon from the body and the silicon object. The additional silicon from the object in the plasma influences the silicon removal from the body to thereby provide tapered trench side walls.

摘要翻译： 在硅体中蚀刻紧密间隔的沟槽的方法，其中将掩模的硅体引入等离子体蚀刻装置中。 在该装置中设置有具有由等离子体环境消耗的暴露的硅表面的物体。 在从身体和硅物体中去除硅的装置中建立了反应等离子体环境。 来自等离子体中的物体的附加硅影响硅体从硅体移除，从而提供锥形的沟槽侧壁。

公开(公告)号：US07253112B2

公开(公告)日：2007-08-07

申请号：US10915633

申请日：2004-08-10

申请人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

发明人： Bang-Chien Ho ,  Jian-Hong Chen ,  Tsang-Jiuh Wu ,  Li-Te Lin ,  Li-Chih Chao ,  Hua-Tai Lin ,  Shyue-Sheng Lu

IPC分类号： H01L21/311

CPC分类号： H01L21/76808

摘要： A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.

摘要翻译： 使用双镶嵌工艺制造半导体器件的方法来在由各种高蚀刻材料和底部抗反射涂层（BARC）材料组成的通孔中形成插塞。 在通孔蚀刻之后，旋涂一层高蚀刻速率的塞材料以填充通孔。 接下来，施加一层光致抗蚀剂。 然后将光致抗蚀剂通过掩模曝光并显影以形成蚀刻开口。 使用剩余的光致抗蚀剂作为蚀刻掩模和底部防反射涂层（BARC）作为保护，氧化物或低k层被蚀刻以形成后续布线。 蚀刻步骤被称为镶嵌蚀刻步骤。 去除剩余的光致抗蚀剂，并且通过金属形成金属互连布线和接触通孔填充沟槽/通孔开口。

公开(公告)号：US06797630B1

公开(公告)日：2004-09-28

申请号：US10184735

申请日：2002-06-28

申请人： Tsang-Jiuh Wu ,  Chen-Nan Yeh ,  Li-Te S. Lin ,  Li-Chih Chao

发明人： Tsang-Jiuh Wu ,  Chen-Nan Yeh ,  Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L21311

CPC分类号： H01L21/76811 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76813 ,  H01L2221/1021

摘要： A method for forming a dual damascene opening comprising the following steps. A structure having an exposed conductive structure formed therein is provided. An etch stop layer is formed over the structure and the exposed conductive structure. A dielectric layer is formed over the etch stop layer. A hard mask layer is formed over the dielectric layer. The hard mask layer is patterned to form a partially opened hard mask layer. The partially opened hard mask layer having a trench area and a via area. The partially opened hard mask layer within the via area is patterned to form a partial via opened hard mask layer. Simultaneously, the partial via opened hard mask layer within both the trench area and the via area are etched and removed, and the dielectric layer within the via area is partial etched to form a partially opened dielectric layer to: expose a portion of dielectric layer within the trench area; and form a partial via within the partially opened dielectric layer. The partially opened dielectric layer is etched: within the trench area to form a trench; and within the via area to form a final via exposing a portion of etch stop layer. The trench and the final via forming the dual damascene opening.

摘要翻译： 一种用于形成双镶嵌开口的方法，包括以下步骤。 提供了一种其中形成有暴露的导电结构的结构。 在结构和暴露的导电结构之上形成蚀刻停止层。 在蚀刻停止层上方形成介电层。 在电介质层上形成硬掩模层。 图案化硬掩模层以形成部分打开的硬掩模层。 部分打开的硬掩模层具有沟槽区域和通孔区域。 将通孔区域内的部分打开的硬掩模层图案化以形成部分通孔打开的硬掩模层。 同时蚀刻去除在沟槽区域和通孔区域内的部分通孔打开的硬掩模层，并且将通孔区域内的电介质层部分地蚀刻以形成部分打开的电介质层，以使其内部的介电层的一部分露出 沟渠区域; 并且在部分打开的电介质层内形成部分通孔。 蚀刻部分开放的电介质层：在沟槽区域内形成沟槽; 并且在通孔区域内，通过暴露一部分蚀刻停止层形成最终的通孔。 沟槽和最后通孔形成双镶嵌开口。

公开(公告)号：US06720256B1

公开(公告)日：2004-04-13

申请号：US10309428

申请日：2002-12-04

申请人： Tsang-Jiuh Wu ,  Li-Te S. Lin ,  Li-Chih Chao

发明人： Tsang-Jiuh Wu ,  Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： An improved method of patterning photoresist during formation of damascene structures is provided which involves a process that is resistant to poisoning from adjacent layers. An inert resin is used to fill vias in a damascene stack. Then a second stack comprised of an underlayer, a non-photosensitive Si-containing layer, an ARC, and a photoresist are formed on the first stack. A trench pattern formed in the photoresist is etch transferred into the first stack. The Si-containing layer that is preferably a spin-on material can be optimized for thermal and etch resistance without compromising lithographic properties since it is not photosensitive. The state of the art photoresist provides a large process window for printing small features with no scum. The inert resin, underlayer, and silicon containing layers are independent of exposure wavelength and can be readily implemented into existing or future manufacturing schemes.

摘要翻译： 提供了一种在形成镶嵌结构期间图案化光刻胶的改进方法，该方法涉及耐相邻层中毒的方法。 使用惰性树脂填充镶嵌叠层中的通孔。 然后在第一叠层上形成由底层，非感光性含硅层，ARC和光致抗蚀剂构成的第二叠层。 在光致抗蚀剂中形成的沟槽图案被蚀刻转移到第一堆叠中。 优选为旋涂材料的含Si层可以针对耐热和耐蚀刻性而优化，而不损害光刻性能，因为它不是光敏的。 最先进的光致抗蚀剂提供了用于打印没有浮渣的小特征的大的工艺窗口。 惰性树脂，底层和含硅层独立于曝光波长，并且可以容易地实现到现有或将来的制造方案中。

公开(公告)号：US06551938B1

公开(公告)日：2003-04-22

申请号：US10056979

申请日：2002-01-25

申请人： Tsang-Jiuh Wu ,  Li-Te S. Lin ,  Li-Chih Chao

发明人： Tsang-Jiuh Wu ,  Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L21311

CPC分类号： H01L21/0332 ,  G03F7/075 ,  G03F7/095 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31138

摘要： A method of bi-layer top surface imaging, comprising the following steps. A structure having a lower layer formed thereover is provided. An upper silicon-containing photoresist layer is formed upon the lower layer. The upper silicon-containing photoresist layer is selectively exposed to form upper silicon-containing photoresist layer exposed portions. The upper silicon-containing photoresist layer exposed portions and the portions of the lower layer below the upper silicon-containing photoresist layer exposed portions are removed using an O2-free N2/H2 plasma etch.

摘要翻译： 一种双层顶面成像方法，包括以下步骤。 提供了一种其上形成有下层的结构。 上层含硅光致抗蚀剂层形成在下层。 选择性地暴露上部含硅光致抗蚀剂层以形成上部含硅光致抗蚀剂层暴露部分。 使用无O2的N 2 / H 2等离子体蚀刻去除上部含硅光致抗蚀剂层暴露部分和下部上部含硅光致抗蚀剂层暴露部分下方的部分。

公开(公告)号：US06429119B1

公开(公告)日：2002-08-06

申请号：US09405059

申请日：1999-09-27

申请人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

发明人： Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui ,  Jen-Cheng Liu ,  Chao-Cheng Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/76813 ,  H01L2221/1063

摘要： Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching. One of the main approaches use self-aligned dual damascene (SADD) etching which requires a thick trench etching stop-layer thickness. The other approach use counter-bore method which requires a thick via etching stop-layer thickness. This invention describes a novel dual damascene process which can minimize the thickness of both via and trench etching stop-layer, while avoiding deleterious damage to the underlying to and via facet profile during via and trench etching.

摘要翻译： 使用这种特殊的双镶嵌工艺，形成具有低寄生电容（低RC时间常数）的互连导线和通孔触点。 本发明包括使用薄蚀刻停止层或蚀刻阻挡层。 本发明的关键工艺步骤是特殊的部分通孔蚀刻和特殊通孔衬垫。 现有技术的双镶嵌工艺通常由厚的通孔蚀刻停止层组成，以避免在通孔图案化期间损坏下面的铜，以及在沟槽图案化期间避免通孔小面的厚沟槽蚀刻停止层。 与氧化硅（金属间电介质（IMD））相比，由于高的介电常数值，厚的蚀刻停止层是不期望的。 因此，应该减小停止层的厚度以最小化电路（RC）时间常数延迟。 一般来说，双镶嵌蚀刻有两种主要方法。 主要方法之一使用自对准双镶嵌（SADD）蚀刻，其需要厚沟槽蚀刻停止层厚度。 另一种方法使用需要厚通孔蚀刻停止层厚度的反孔法。 本发明描述了一种新颖的双镶嵌工艺，其可以最小化通孔和沟槽蚀刻停止层的厚度，同时避免在通孔和沟槽蚀刻期间对于底面和经过小面轮廓的有害损伤。

公开(公告)号：US06376366B1

公开(公告)日：2002-04-23

申请号：US09860371

申请日：2001-05-21

申请人： Li-Te S. Lin ,  Li-Chih Chao

发明人： Li-Te S. Lin ,  Li-Chih Chao

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76813 ,  Y10S438/942

摘要： A method is provided for forming dual damascene structures with a partial hard mask through a judicious use of partial opening or etching of the mask which simplifies the dual damascene process, and makes it especially suitable for low-k dielectric materials in advanced sub-micron technologies capable of forming features approaching less than 0.10 micrometers (&mgr;m). This is accomplished by forming a hard mask over a low-k dielectric layer. The hard mask is first opened partially to form a trench, and later again to form a via opening. The via opening is next extended into the low-k dielectric layer, followed by etching further the partial trench into the hard mask, and then transferring the trench pattern into the dielectric layer while at the same time extending the via opening to the underlying metal layer.

摘要翻译： 提供了通过明智地使用掩模的部分打开或蚀刻来形成具有部分硬掩模的双镶嵌结构的方法，其简化了双镶嵌工艺，并且使其特别适用于先进亚微米技术中的低k电介质材料 能够形成接近小于0.10微米（mum）的特征。 这是通过在低k电介质层上形成硬掩模来实现的。 首先将硬掩模部分地打开以形成沟槽，然后再次形成通孔。 通孔开口接下来延伸到低k电介质层中，随后将部分沟槽进一步蚀刻到硬掩模中，然后将沟槽图案转移到电介质层中，同时将通孔开口延伸到下面的金属层 。