公开(公告)号：US5511024A

公开(公告)日：1996-04-23

申请号：US201981

申请日：1994-02-25

申请人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

发明人： Frederick A. Ware ,  John B. Dillon ,  Richard M. Barth ,  Billy W. Garrett, Jr. ,  John G. Atwood, Jr. ,  Michael P. Farmwald

IPC分类号： G06F13/16 ,  G11C5/06 ,  G11C11/401 ,  G06F1/12

CPC分类号： G11C5/066

摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

公开(公告)号：US08199859B2

公开(公告)日：2012-06-12

申请号：US12897661

申请日：2010-10-04

申请人： Jared L. Zerbe ,  Bruno W. Garlepp ,  Pak S. Chau ,  Kevin S. Donnelly ,  Mark A. Horowitz ,  Stefanos Sidiropoulos ,  Billy W. Garrett, Jr. ,  Carl W. Werner

发明人： Jared L. Zerbe ,  Bruno W. Garlepp ,  Pak S. Chau ,  Kevin S. Donnelly ,  Mark A. Horowitz ,  Stefanos Sidiropoulos ,  Billy W. Garrett, Jr. ,  Carl W. Werner

IPC分类号： H03D1/24 ,  H03K7/02

CPC分类号： H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

摘要： An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

摘要翻译： 集成电路器件包括具有输入端的读出放大器，用于接收表示当前位的当前信号。 读出放大器将产生关于当前位的逻辑电平的判定。 该集成电路器件还包括一个电路，用于通过向读出放大器的输入端施加代表先前位的先前信号的一部分来对读出放大器的输入进行预充电。 集成电路器件还包括耦合到读出放大器以输出逻辑电平的锁存器。

公开(公告)号：US07536494B2

公开(公告)日：2009-05-19

申请号：US11752242

申请日：2007-05-22

申请人： Bruno W. Garlepp ,  Richard M. Barth ,  Kevin S. Donnelly ,  Ely K. Tsern ,  Craig E. Hampel ,  Jeffrey D. Mitchell ,  James A. Gasbarro ,  Billy W. Garrett, Jr. ,  Fredrick A. Ware ,  Donald V. Perino

发明人： Bruno W. Garlepp ,  Richard M. Barth ,  Kevin S. Donnelly ,  Ely K. Tsern ,  Craig E. Hampel ,  Jeffrey D. Mitchell ,  James A. Gasbarro ,  Billy W. Garrett, Jr. ,  Fredrick A. Ware ,  Donald V. Perino

IPC分类号： G06F13/36

CPC分类号： G06F13/4072 ,  G06F13/4086 ,  G06F13/4243

摘要： A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.

摘要翻译： 系统包括第一总线，耦合到第一总线的主设备和耦合到第一总线的一个或多个子系统。 相应的子系统包括第二总线，耦合到第二总线的一个或多个从设备，写入缓冲器，用于经由第一总线接收来自主设备的输入信号，以及经由第二总线将信号发送到一个或多个从设备 响应于输入信号，以及读缓冲器，用于经由第二总线接收来自一个或多个从设备的输出信号，并响应于输出信号经由第一总线向主设备发送信号。

公开(公告)号：US07222209B2

公开(公告)日：2007-05-22

申请号：US10738293

申请日：2003-12-16

申请人： Bruno W. Garlepp ,  Richard M. Barth ,  Kevin S. Donnelly ,  Ely K. Tsern ,  Craig E. Hampel ,  Jeffrey D. Mitchell ,  James A. Gasbarro ,  Billy W. Garrett, Jr. ,  Fredrick A. Ware ,  Donald V. Perino

发明人： Bruno W. Garlepp ,  Richard M. Barth ,  Kevin S. Donnelly ,  Ely K. Tsern ,  Craig E. Hampel ,  Jeffrey D. Mitchell ,  James A. Gasbarro ,  Billy W. Garrett, Jr. ,  Fredrick A. Ware ,  Donald V. Perino

IPC分类号： G06F13/14

CPC分类号： G06F13/4072 ,  G06F13/4086 ,  G06F13/4243

摘要： A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

摘要翻译： 与可寻址存储器一起使用的总线系统具有双向信号线的全局总线。 全球总线有一个第一端和一端。 主设备在第一端向全局总线发送数据并从其接收数据。 全局总线终端器在第二端耦合到全局总线。 一个或多个从设备，包括与主设备最远距离的最后一个从设备，每个包括耦合到全局总线的至少一些双向信号线的有源终端器。 只有最后一个从设备的活动终端才能使能。

公开(公告)号：US4987551A

公开(公告)日：1991-01-22

申请号：US421316

申请日：1989-11-24

申请人： Billy W. Garrett, Jr.

发明人： Billy W. Garrett, Jr.

IPC分类号： G06F3/153 ,  G09G1/00 ,  G09G1/24 ,  G09G5/08

CPC分类号： G09G5/08

摘要： An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor outline and pattern information. The cursor data is accessed from the non-displayed segment of the memory during horizontal blank time preceding the raster scan of the video pattern data subject to cursor overlay. Thereby, the video pattern data in the frame buffer and cursor data are arranged by scan or row line. The column location of the cursor pattern is defined by the computer and stored in a position counter to be synchronously incremented by pixel during the scan of the frame buffer line. At the appropriate count the cursor data is logically combined with frame buffer pattern data to superimpose the cursor characteristics upon the video pattern data. The cursor data buffer can thereby be relatively small yet overlay a relatively large cursor with minimal manipulation by the computer controlling the video display.

摘要翻译： 一种用于在从具有非显示但可寻址的存储器空间的帧缓冲器中操作的位映射视频显示系统的上下文中生成硬件光标的架构。 未显示的存储器的段被加载光标大纲和模式信息。 在光标覆盖的视频图案数据的光栅扫描之前的水平空白时间期间，从存储器的未显示段访问光标数据。 由此，帧缓冲器中的视频图形数据和光标数据通过扫描或行行排列。 光标图案的列位置由计算机定义并存储在位置计数器中，以在帧缓冲器线的扫描期间被同步递增像素。 在适当的计数下，光标数据与帧缓冲器模式数据逻辑组合，以将光标特性叠加在视频图形数据上。 因此，光标数据缓冲器可以相对较小，但是通过控制视频显示的计算机的最小化操作覆盖相对大的光标。