-
公开(公告)号:US06687780B1
公开(公告)日:2004-02-03
申请号:US09706238
申请日:2000-11-02
申请人: Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
发明人: Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
IPC分类号: G06F1340
CPC分类号: G06F13/4072 , G06F13/4086 , G06F13/4243
摘要: A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel to each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.
摘要翻译: 与可寻址存储器一起使用的总线系统具有单向信号线的全局总线。 全球总线有一个第一端和一端。 主设备向全局总线发送数据并从全局总线接收数据。 第一和第二全局总线终端分别耦合到全局总线的第一和第二端。 一个或多个子系统通过全局总线彼此并联连接到主设备。 每个子系统包括本地总线,耦合到本地总线的一个或多个从设备,经由全局总线接收来自主设备的输入信号的写入缓冲器,并且经由本地总线将输入信号发送到一个或多个从设备, 以及读取缓冲器,其经由本地总线从一个或多个从设备接收输出信号,并经由全局总线将输出信号发送到主设备。
-
公开(公告)号:US07536494B2
公开(公告)日:2009-05-19
申请号:US11752242
申请日:2007-05-22
申请人: Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
发明人: Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
IPC分类号: G06F13/36
CPC分类号: G06F13/4072 , G06F13/4086 , G06F13/4243
摘要: A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.
摘要翻译: 系统包括第一总线,耦合到第一总线的主设备和耦合到第一总线的一个或多个子系统。 相应的子系统包括第二总线,耦合到第二总线的一个或多个从设备,写入缓冲器,用于经由第一总线接收来自主设备的输入信号,以及经由第二总线将信号发送到一个或多个从设备 响应于输入信号,以及读缓冲器,用于经由第二总线接收来自一个或多个从设备的输出信号,并响应于输出信号经由第一总线向主设备发送信号。
-
公开(公告)号:US07222209B2
公开(公告)日:2007-05-22
申请号:US10738293
申请日:2003-12-16
申请人: Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
发明人: Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
IPC分类号: G06F13/14
CPC分类号: G06F13/4072 , G06F13/4086 , G06F13/4243
摘要: A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.
摘要翻译: 与可寻址存储器一起使用的总线系统具有双向信号线的全局总线。 全球总线有一个第一端和一端。 主设备在第一端向全局总线发送数据并从其接收数据。 全局总线终端器在第二端耦合到全局总线。 一个或多个从设备,包括与主设备最远距离的最后一个从设备,每个包括耦合到全局总线的至少一些双向信号线的有源终端器。 只有最后一个从设备的活动终端才能使能。
-
公开(公告)号:US08634452B2
公开(公告)日:2014-01-21
申请号:US13491508
申请日:2012-06-07
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
IPC分类号: H04B17/00
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.
摘要翻译: 集成电路装置包括:第一电路,用于接收与电输入信号的第一数据周期相关联的位,可操作以产生关于与第一数据周期相关联的位的逻辑状态的判定;以及第二电路,用于接收与第 电输入信号的第二周期,以产生关于与第二数据周期相关联的位的逻辑状态的判定。 均衡电路根据第一电路的输出补偿影响第二电路的符号间干扰,并根据第一电路以外的电路的输出补偿影响第一电路的符号间干扰,该电路可操作以产生关于位的逻辑状态的判定 的电气输入信号。
-
公开(公告)号:US07124221B1
公开(公告)日:2006-10-17
申请号:US09478916
申请日:2000-01-06
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
摘要翻译: 存储系统使用多脉冲幅度调制(多PAM)输出驱动器和接收器来发送和接收多PAM信号。 多PAM信号具有两个以上的电压电平,每个数据间隔现在以有效电压电平之一发送“符号”。 在一个实施例中,符号表示两个或更多位。 多PAM输出驱动器将输出符号驱动到信号线上。 输出符号表示包括最高有效位(MSB)和最低有效位(LSB)的至少两个位。 多PAM接收器从信号线接收输出符号,并确定MSB和LSB。
-
公开(公告)号:US07809088B2
公开(公告)日:2010-10-05
申请号:US12624365
申请日:2009-11-23
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.
摘要翻译: 用于补偿输入信号采样中的符号间干扰的多相接收机包括:第一积分接收器,用于在时钟的第一相位上对输入信号的数据进行积分和采样;以及第二积分接收器,对输入信号的数据进行积分和采样 在时钟的第二阶段。 多相接收机还包括均衡电路,用于根据先前由不同于第一积分接收器的积分接收器接收的数据的积分结果来调整由第一积分接收器的积分,并根据结果调整由第二积分接收器的积分 对由先前由不同于第二积分接收器的积分接收器接收的数据的积分。
-
公开(公告)号:US07626442B2
公开(公告)日:2009-12-01
申请号:US11368012
申请日:2006-03-03
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
摘要翻译: 存储系统使用多个脉冲幅度调制(多PAM)输出驱动器和接收器来发送和接收多PAM信号。 多PAM信号具有两个以上的电压电平,每个数据间隔现在以有效电压电平之一发送“符号”。 在一个实施例中,符号表示两个或更多位。 多PAM输出驱动器将输出符号驱动到信号线上。 输出符号表示包括最高有效位(MSB)和最低有效位(LSB)的至少两个位。 多PAM接收器从信号线接收输出符号并确定MSB和LSB。
-
公开(公告)号:US08199859B2
公开(公告)日:2012-06-12
申请号:US12897661
申请日:2010-10-04
申请人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人: Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
CPC分类号: H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.
摘要翻译: 集成电路器件包括具有输入端的读出放大器,用于接收表示当前位的当前信号。 读出放大器将产生关于当前位的逻辑电平的判定。 该集成电路器件还包括一个电路,用于通过向读出放大器的输入端施加代表先前位的先前信号的一部分来对读出放大器的输入进行预充电。 集成电路器件还包括耦合到读出放大器以输出逻辑电平的锁存器。
-
公开(公告)号:US06898085B2
公开(公告)日:2005-05-24
申请号:US10695854
申请日:2003-10-30
申请人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
发明人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
IPC分类号: G06F13/40 , G11C5/00 , H05K1/02 , H05K1/11 , H05K1/14 , H05K7/06 , H05K7/14 , H05K7/02 , H05K7/10
CPC分类号: G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
-
公开(公告)号:US06765800B2
公开(公告)日:2004-07-20
申请号:US09839642
申请日:2001-04-20
申请人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
发明人: Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
IPC分类号: H05K702
CPC分类号: G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译: 公开了可用于实现具有1至N个信道的模块的各种模块结构。 总线系统可以通过这种模块的互连形成。
-
-
-
-
-
-
-
-
-