公开(公告)号：US4803657A

公开(公告)日：1989-02-07

申请号：US43384

申请日：1987-04-28

申请人： Burkhard Giebel ,  Ulrich Theus

发明人： Burkhard Giebel ,  Ulrich Theus

IPC分类号： G11C7/00 ,  G06F5/08 ,  G11C19/00 ,  G11C19/18 ,  G11C19/28

CPC分类号： G06F5/08 ,  G11C19/188

摘要： A delay line digital memory is organized into n signal branches (z.sub.1 . . . z.sub.n), each with m cells which form a serial data or signal flow path. Each cell is comprised of a transfer transistor t with a subsequently following level restorer, regenerator, or buffer circuit p which, however, is omitted in the last cell. Furthermore, n clock signals (s.sub.l . . . s.sub.n) are provided whose frequency (or repetition rate) equals one n-th of the data rate of the digital input signals, and whose effective pulses follow each other in temporal serial succession within one period of the data rate. Clocking (or activation) by clock signals (s.sub.1 . . . s.sub.n) is chosen so that in the first signal branch (z.sub.1) the first transistor is fed with the last clock signal (s.sub.n); in the second signal branch, the first transistor is fed with the next to last clock signal (s.sub.n-1); in the next to last signal branch (z.sub.n-1), the first transistor is fed with the second clock signal (s.sub.2); and in the 1st signal branch (z.sub.n) the first transistor is fed with the first clock signal (s.sub.1) at its gate. The remaining transistors of each signal branch are then fed in the sense of a descending clock-signal numbering order. Both the inputs and outputs of the signal branches are assembled or led together to either the signal input (s.sub.e) or the signal output (s.sub.a). This arrangement results in a considerable saving of space in the case of a monolithic integration compared to the cases in which shift registers or dynamic random access memories (DRAMs) are employed. The effective length of the storage time can be reduced in increments corresponding to the magnitude of the period of the data rate of the input signal.

摘要翻译： 延迟线数字存储器被组织成n个信号分支（z1 ... zn），每个信号分支具有形成串行数据或信号流路径的m个单元。 每个单元由具有随后的下一级恢复器，再生器或缓冲电路p的传输晶体管t组成，然而在最后一个单元中省略。 此外，提供了n个时钟信号（s1·sn），其频率（或重复频率）等于数字输入信号的数据速率的十分之一，并且其有效脉冲在一个周期内以时间序列连续相互追随 的数据速率。 选择由时钟信号（s1，...）进行的时钟（或激活），使得在第一信号分支（z1）中，第一晶体管馈送最后的时钟信号（sn）; 在第二信号分支中，第一晶体管馈送有下一个最后的时钟信号（sn-1）; 在下一个信号分支（zn-1）中，第一晶体管馈送第二时钟信号（s2）; 并且在第一信号分支（zn）中，第一晶体管在其门处馈送有第一时钟信号（s1）。 然后每个信号分支的剩余晶体管以降序的时钟信号编号顺序被馈送。 信号分支的输入和输出都被组合或者被引导到信号输入（se）或信号输出（sa）。 与使用移位寄存器或动态随机存取存储器（DRAM）的情况相比，这种布置导致在单片集成的情况下相当大的节省空间。 存储时间的有效长度可以以与输入信号的数据速率的周期的大小对应的增量减小。

公开(公告)号：US07293120B2

公开(公告)日：2007-11-06

申请号：US10751668

申请日：2004-01-05

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： A DMA module includes an address generator to perform a write or read access to a location of an addressable memory, and an address counter to advance a stored address to an adjacent memory location. The address counter does not act on an internal register of the DMA module but instead is configured so that between reading an address value from the memory and writing the address value to the memory, the address counter is advanced once. The memory location at which the address value is read or written takes on the function of a register conventionally integrated in the DMA module. This approach reduces the space requirement of the DMA module, and the DMA module may be employed to control a large number of DMA processes that may mutually interrupt each other by providing a plurality of memory locations to store specifications of the DMA blocks.

摘要翻译： DMA模块包括地址发生器，用于执行对可寻址存储器的位置的写入或读取访问，以及地址计数器，用于将存储的地址推进到相邻存储器位置。 地址计数器不对DMA模块的内部寄存器起作用，而是配置为在从存储器读取地址值并将地址值写入存储器之前，地址计数器被提前一次。 读取或写入地址值的存储器位置具有常规集成在DMA模块中的寄存器的功能。 这种方法减少了DMA模块的空间需求，并且可以采用DMA模块来控制可以通过提供多个存储器位置来存储DMA块的规范来相互中断的大量DMA进程。

公开(公告)号：US5326994A

公开(公告)日：1994-07-05

申请号：US955765

申请日：1992-10-02

申请人： Burkhard Giebel ,  Wilfried W. Gehrig

发明人： Burkhard Giebel ,  Wilfried W. Gehrig

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/74 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/0251 ,  H01L27/0248

摘要： A protective circuit for connecting contacts of monolithic integrated circuits, particularly CMOS input/output stages. The protective circuit has a four-layer device (ta, ts) with a defined switching threshold in the area of each connecting contact (A) and a low-resistivity current path (sa) from the connecting contact (A) to a supply terminal (VSS, VDD). The protective circuit also contains devices (zw2, z5) which prevent or provide a bypass for any undesired flow of current (i3, i4) between at least parts of the four-layer device and triggerable circuit regions (W2).

摘要翻译： 用于连接单片集成电路的触点的保护电路，特别是CMOS输入/输出级。 保护电路具有在每个连接触点（A）的区域中具有确定的开关阈值的四层器件（ta，ts）和从连接触点（A）到电源端子的低电阻率电流通路（sa） （VSS，VDD）。 保护电路还包含用于在四层器件和可触发电路区域（W2）的至少部分之间防止或提供任何不期望的电流（i3，i4）的旁路的器件（zw2，z5）。

公开(公告)号：US4750158A

公开(公告)日：1988-06-07

申请号：US461791

申请日：1983-01-28

申请人： Burkhard Giebel ,  Thomas Fischer

发明人： Burkhard Giebel ,  Thomas Fischer

IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C29/789 ,  G11C29/822

摘要： In an integrated matrix of nonvolatile, reprogrammable storage cells, additional memory is provided to replace defective rows of storage cells. The addresses of the defective rows are stored in a region of the matrix. A correction register can be loaded with the addresses of the defective rows from the region of the matrix when power is first applied to the matrix or whenever the applied power deviates from the expected, nominal value.

摘要翻译： 在非易失性可再编程存储单元的集成矩阵中，提供了附加存储器来代替存储单元的有缺陷的行。 有缺陷的行的地址存储在矩阵的区域中。 当功率首次施加到矩阵时或每当施加的功率偏离预期的标称值时，校正寄存器可以从矩阵的区域加载有缺陷行的地址。

公开(公告)号：US4597064A

公开(公告)日：1986-06-24

申请号：US518239

申请日：1983-07-28

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C16/02 ,  G11C16/08 ,  G11C16/10 ,  G11C8/00

CPC分类号： G11C16/08 ,  G11C16/10

摘要： An electrically programmable memory matrix comprises electrically programmable memory cells arranged in columns and rows, each consisting of a source-drain series arrangement of a memory transistor with a select transistor. The gate of the select transistor may be connected to one of row selecting lines of a row decoder, to which there are connected all gates of one row of the selected transistors of the memory cells of the same row. Control gates of groups of memory transistors (Ts) of one row may be connected to one common programming line, with these programming lines being connected by blocks via each time one group select transistor to one common block line which, via the source-drain line of a block select transistor whose gate is connected to one of a plurality of outputs of a block decoder is connected to one source of block signals. Re-programmability of a fixed number of memory cells only upon application of a further input signal, apart from a function signal, is accomplished by subdividing at least one of the two decoders into a first decoder part to the function signal input of which the programming signal is applied directly, and into a second decoder part whose function signal input is connected to the output of a gate circuit having two inputs. Th output signal of the gate circuit is only then at the value corresponding to the function "programming" when the first input is also at the value corresponding to the function "programming", and when the second input is at that particular value which permits a programming of the second decoder part.

摘要翻译： 电可编程存储器矩阵包括以列和行排列的电可编程存储单元，每一个由具有选择晶体管的存储晶体管的源 - 漏串联布置组成。 选择晶体管的栅极可以连接到行解码器的行选择线之一，其中连接同一行的存储器单元的所选晶体管的一行的所有栅极。 一行的存储晶体管（Ts）的组的控制栅极可以连接到一个公共编程线，这些​​编程线通过每个一个组选择晶体管通过块连接到一个公共块线，其经由源极 - 漏极线 其栅极连接到块解码器的多个输出中的一个的块选择晶体管连接到块信号的一个源。 除了功能信号之外，仅在施加另外的输入信号时，固定数量的存储器单元的可重新编程通过将两个解码器中的至少一个分解为第一解码器部分来实现，该第一解码器部分编程为功能信号输入 信号直接施加到第二解码器部分，其功能信号输入连接到具有两个输入的门电路的输出。 当第一输入也处于与功能“编程”相对应的值时，门电路的Th输出信号仅处于对应于功能“编程”的值，并且当第二输入处于允许 第二解码器部分的编程。

公开(公告)号：US4527256A

公开(公告)日：1985-07-02

申请号：US470759

申请日：1983-02-28

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： G11C29/00 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C17/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

摘要： EEPROM showing storage cells comprising a tunnel injector which at the one hand is connected to a first bit line by means of the source-drain-line of a floating gate FET and at the other hand to a second bit line by means of the source-drain-line of a selection FET. Interferences between addressed groups and not addressed groups of storage cells during writing are eliminated by means of connection of the first bitline of the not addressed groups via the source-drain-lines of a depletion type FET and an enhancement FET to ground.

摘要翻译： EEPROM显示包括隧道注射器的存储单元，其一方面通过浮置栅极FET的源极 - 漏极线连接到第一位线，另一方面通过源极 - 漏极连接到第二位线， 选择FET的漏极线。 借助于经由耗尽型FET和增强型FET的源极 - 漏极到地的非寻址组的第一位线的连接来消除写入期间寻址组和未寻址组的存储单元之间的干扰。

公开(公告)号：US4524429A

公开(公告)日：1985-06-18

申请号：US472349

申请日：1983-03-04

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C29/00 ,  G11C29/12 ,  G11C29/50 ,  G11C11/40

CPC分类号： G11C29/50 ,  G11C16/0433 ,  G06F2201/81 ,  G11C16/04

摘要： The invention discloses an integrated memory matrix comprising nonvolatile reprogrammable storage (memory) cells arranged in rows and columns, as well as a classifying circuit integrated as well in the semiconductor body of the memory matrix, containing a nonprogrammable reference storage cell (Mr) of the same construction as that of the storage cells, and which is manufactured simultaneously as a comparison standard, with the storage cells. With the aid of a first voltage divider (Q1) integrated as well, whose output voltage is adjustable in steps, and whose output current is fed into the source-drain line of the reference storage cell (Mr) and/or of a second voltage divider (Q2) adjustable in steps and integrated as well, whose output voltage is applied to the control gate of the storage transistor (Ts) of the reference storage cell (Mr), it is possible to simulate a threshold voltage which is compared with the threshold voltages of the storage cells (M11 . . . Mmn) of the memory matrix (S) either individually or in groups with the aid of a comparator circuit (Ad) for obtaining a classifying criterion.

摘要翻译： 本发明公开了一种集成存储器矩阵，其包括排列成行和列的非易失性可再编程存储（存储器）单元，以及集成在存储器矩阵的半导体本体中的分类电路，其包含不可编程的参考存储单元 与存储单元的构造相同，并且作为比较标准与存储单元同时制造。 借助于集成的第一分压器（Q1），其输出电压可以步进地调节，并且其输出电流被馈送到参考存储单元（Mr）的源极 - 漏极线和/或第二电压 分压器（Q2）可以步进调节并集成，其输出电压施加到参考存储单元（Mr）的存储晶体管（Ts）的控制栅极，可以模拟与 借助于用于获得分类标准的比较器电路（Ad），单独地或分组地存储矩阵（S）的存储单元（M11 ... Mmn）的阈值电压。

公开(公告)号：US4922139A

公开(公告)日：1990-05-01

申请号：US312263

申请日：1989-02-21

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： H03L7/093 ,  H03L7/089

CPC分类号： H03L7/0895

摘要： A filter circuit is driven by two digital phase responsive output signals from the frequency/phase discriminator of a phase-locked loop (PLL) circuit. The controlled current paths of a first n-conducting transistor, a second n-conducting transistor, a second p-conducting transistor and a first p-conducting transistor are connected in that order between the plus and minus poles of a source of supply voltage. The common connection between the controlled current paths of the second n-conducting transistor and the second p-conducting transistor is connected to the output of the filter circuit. The second n-conducting transistor and the second p-conducting transistor are connected as diodes with the gate of the second n-conducting transistor connected to the common connection between the first n-conducting transistor and the second n-conducting transistor, and with the gate of the second p-conducting transistor connected to the common connection between the first p-conducting transistor and the second p-conducting transistor. The output of the filter circuit is connected across a series RC circuit to the minus pole of the source of supply voltage. The first digital signal from the frequency/phase discriminator is fed to the gate of the second n-conducting transistor via a capacitor. The second digital signal from the frequency/phase discriminator is fed to the gate of the second p-conducting transistor via the series arrangement of an inverter and a capacitor. The gate of the first n-conducting transistor and the gate of the first p-conducting transistor are applied to the common connection of the resistor and the capacitor of the RC circuit. In that way the range of control of the output voltage from the filter circuit is substantially greater than that of the supply voltage, and the coupling-in of the two digital signals to the output voltage is substantially avoided.

公开(公告)号：US4733394A

公开(公告)日：1988-03-22

申请号：US855141

申请日：1986-04-23

申请人： Burkhard Giebel

发明人： Burkhard Giebel

IPC分类号： G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/44 ,  G11C29/50 ,  G01R31/28

CPC分类号： G11C29/76 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/82 ,  G06F2201/81 ,  G11C16/04 ,  G11C29/44

摘要： An integrated memory system includes a microcomputer which, at defined intervals and by employing a classifying circuit integrated in an EEPROM, checks the memory cells of the EEPROM with respect to variations of the threshold values. Upon detection of a fault in a row or column which has thus been recognized as being faulty, this faulty row or column whose address is then stored in one EEPROM area, is replaced by a redundant row or column in another area by making use of a correction register.

摘要翻译： 集成存储器系统包括微计算机，其以限定的间隔并通过采用集成在EEPROM中的分类电路，相对于阈值的变化检查EEPROM的存储单元。 在检测到由此被认定为有故障的行或列中的故障时，将其地址存储在一个EEPROM区域中的该故障行或列被另一区域中的冗余行或列替换，通过使用 校正寄存器。

公开(公告)号：US4459608A

公开(公告)日：1984-07-10

申请号：US364886

申请日：1982-04-02

申请人： Burkhard Giebel ,  Adolf Scheibe

发明人： Burkhard Giebel ,  Adolf Scheibe

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L29/7883

摘要： Reprogrammable semiconductor read-only memory with memory cells of the floating-gate type, including an additional potential carrier for each memory cell for capacitively coupling a further potential to the floating gate.

摘要翻译： 具有浮栅型存储单元的可再编程半导体只读存储器，包括用于将另外的电位电容耦合到浮置栅极的每个存储单元的附加电位载波。